Servizio Comunitario di Informazione in materia di Ricerca e Sviluppo - CORDIS

FP5

CODESTAR Sintesi della relazione

Project ID: IST-2001-34058
Finanziato nell'ambito di: FP5-IST
Paese: Belgium

Deep submicron interconnect technology using low-K materials

The Codestar solver allows to analyze and predict the high frequency performance of advanced interconnect architectures. The required input consists of interconnect geometry (layout, wire dimensions, dielectric thickness), material properties (wire resistivity, dielectric constant and loss tangent) and frequency range of interest.
The provided output is in form of S-parameters or line parameters RCLG per unit length, in function of frequency.

The output allows to predict the interconnect bandwidth in function of the choice of the conductor and insulating materials, and in function of interconnect dimensions. Therefore, it is possible to evaluate the impact of new materials and new technology nodes on signal propagation on ICs.

The further capability to generate a reduced order model based on lumped elements and consistion of a Spice netlist, allows to virtually model any type of interconnect architecture and to analyse its behaviour in time domain.

This opens the possibility of performing "what if" experiments in a short time without having to wait for structures to be implemented on silicon; in many cases, this implementation is made very difficult by very aggressive dimensions and complex architectures. The possibility to predict the interconnect performance allows to evaluate the impact of future technology nodes on signal propagation on ICs.
This type of activity is in the framework of the Imec research program on Advanced Interconnects.

In general, IMEC’s advanced CMOS research targets technology nodes at least two generations ahead of industrial needs. These research activities focus on new materials, process steps and modules, and the demonstration of novel device architectures. The activities are aligned with the overall timing and objectives of the International Technology Roadmap for Semiconductors (ITRS). IC manufacturers, tool and materials suppliers participate in the research programs.

The Advanced Interconnect program focuses on the preparation of the selection of the interconnect technology selection for the 45 and 32nm node by:
a) Finding ways to meet ITRS RC delay specs
- Integrating low-k materials with k < 2.7 and exploring the feasibility of air gap technology
- Investigating mechanisms that determine copper resistivity in narrow dimensions
- Evaluating dielectric reliability, barrier integrity, electromigration and stress induced voiding

b) Developing packaging solutions compatible with Cu/low-k
- Fine pitch wire bonding
- Fine pitch flip chip solutions
- Evaluate reliability of packaging solution

c) Developing above IC interconnect functionality
- Wafer Level Packaged multi level interconnects for high speed signal routing
- Wafer Level Packaged passive components

d) Exploring Novel Interconnect Technologies

The results of the Codestar activity fit in d), but have strong implications in a), b) c) for the performance prediction.

Contatto

Rudi CARTUYVELS, (Division Director)
Tel.: +32-16-281757
Fax: +32-16-281214
E-mail