Forschungs- & Entwicklungsinformationsdienst der Gemeinschaft - CORDIS


MICRON Berichtzusammenfassung

Project ID: IST-2001-33567
Gefördert unter: FP5-IST
Land: Spain

Specific integrated mixed-signal circuit IC for nanotool control

The controller IC (MXS chip) receives instructions and transforms them into control signals to perform the requested action. Actions include the generation of waveforms with different shape and frequency, controlling of the tools with the possibility to use an on-chip PID controller and sending information of the sensors and the microrobot state. These tasks could be executed in a micro-controller. However, a solution based on an ASIC has been selected because is better in terms of area and power consumption. The MXS circuit has been implemented with a 0.35m technology from Austrian Microsystems. The core works at 3.3V and occupies 16mm2. It has 84 pins, but only 27 are used to connect the core with the other robot components. The chip is composed of full custom blocks; specific logic implemented with standard cells and customized IP cores (A/D and D/A converters and a power on reset (POR)). The IPs have been modified to adapt them to the chip requirements.

The controller architecture is a Global Asynchronous Local Synchronous (GALS) architecture to deal with the power restrictions. To develop the GALS architecture, the different clocks are generated by an on-chip programmable clock generator module from a 40MHz clock produced by an external crystal quartz. For each operation mode, the controller generates 1 to 4 control signals O1, O2, O3 and O4, which are amplified by the high voltage drivers (not included in the controller IC). These signals are linear combinations of trapezoidal or saw tooth signals for the carrier and the rotor, whereas triangular for the AFM tip. They are coded in 10 bits to achieve nanometric resolutions, with a maximum resolution of 512 samples per period. The frequency range goes from 0.1Hz for the AFM operation modes to 2kHz for the maximum displacement speed. The number of control signals depends on the piezoelectric element (only one can be active at the same time): 4 for the AFM and the carrier and only 2 for the rotor. The signals can have a phase shift of 0?, 90?, 180? or 270? between them. Programming all these parameters (waveform wav, amplitude Np, sampling frequency Ts, phase and number of samples of the control signals Ns) is possible to execute straight and circular displacements in the carrier mode or to move the arm to position the AFM tip in the rotor mode. The signals are generated in a full period and stored in one of the four independent 512x16 SRAM included.

For the calculation of the waveforms, they are decomposed into straight lines and each segment is calculated by an optimised Bresenham algorithm implemented in hardware. After generation of the waveform signals a 16-bit data-path mixes these signals as a function of the operation mode and outputs them through four 10b D/A converters. During mixing it is possible to apply a programmable gain (Gi) and offset (OFFi) to the signals. The gain Gi and offset OFFi are applied to compensate to the first order the piezoelectric fabrication mismatches for the carrier, rotor, nanoidentation and scanning modes. It also allows compensating the offsets of the high voltage drivers. For experiences requiring a closed loop control a digital PID has been also implemented. The main characteristics for the hardware implementation of the PID are the low power consumption and flexibility. Flexibility is required because several tools in the robot use the same PID hardware (AFM and micropipette). The final architecture of the PID is completely configurable by accessing at the programation registers. The data-path has been reduced to only one 16b adder and one 16b multiplier.

To allow the communication between the robot and a host computer an IRC protocol has been included. It implements protocol wrappers and unwrappers of the physical IrDA protocol layer. Featured data rates range from 9.6kbit/s (SIR) over 1.152Mbit/s (MIR) up to 4Mbit/s (FIR) for flexibility in bandwidth and power consumption. Several IRC submodules can be switched off in order to minimize power input. Additionally, a low power protocol derived from SIR is implemented. CRC sums of up to 32 bits guarantee data integrity. The receiver module RX Unit can adapt to initial frequency deviations of 5% in SIR and MIR, and 2% in FIR mode. Frequency drift, e.g. due to changing working temperature, are compensated for, automatically.

Verwandte Informationen


Ángel DIÉGUEZ, (Associate Professor)
Tel.: +34-93-4039149
Fax: +34-93-4021148
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