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FP5

QUDOS Résumé de rapport

Project ID: IST-2001-32358
Financé au titre de: FP5-IST
Pays: United Kingdom

Design of advanced threshold gate

At the initial stages of the project threshold logic gates and circuits were designed and simulated using models of III/V based RTDS and HFETs. These displayed high speed but were limited in fan-in and fan-out capabilities and as a result were unlikely to be viable at large scale integration. By contrast the circuits simulated for Si/SiGe based ITDs and NMOS/CMOS FETs showed a reduced speed but highly increased fan-in and fan-out. The models developed for the Si/SiGe ITD and high performance NMOSFET showed good correlation with the measured results and circuits

Reported by

UNIVERSITY OF ULSTER
CROMORE ROAD
COLERAINE
United Kingdom
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