Forschungs- & Entwicklungsinformationsdienst der Gemeinschaft - CORDIS

FP5

QUDOS Berichtzusammenfassung

Project ID: IST-2001-32358
Gefördert unter: FP5-IST
Land: Spain

Design and verification of multi-threshold artificial neuron

Two objectives have been focussed in this period: a deeper knowledge of the self-latching feature in MOBILE-based circuits and the development of circuit topologies able to implement generalized threshold logic functions, i.e., Multi-threshold Threshold Gates (MTTGs).

- M.J. Avedillo, J.M. Quintana, H. Petthengui, P. Kelly, C.J.Thomson; Multi-threshold Threshold Logic Circuit Design Using Resonant Tunneling Devices, Electronics Lett., 39, no. 21, pp. 1502-1503, 2003.

- H. Pettenghi, M.J. Avedillo, and J.M. Quintana, A CAD tool for the design of RTD programmable gates based on MOBILE, Proc. Design of Circuits and Integrated Systems Conf. (DCIS'04), pp. 25-30, 2004.

Verwandte Informationen

Reported by

Centro Nacional de Microelectrónica (IMSE-CNM), Inst. de Microelectronica de Sevilla
Avda. Reina Mercedes, s/n
41012 Seville
Spain
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