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ATHIS Résumé de rapport

Project ID: G1RD-CT-2002-00729
Financé au titre de: FP5-GROWTH
Pays: Belgium

LDMOS transistor in thin film fully depleted SOI CMOS 2µm process

A complete study about behaviour and capability in DC mode for the LDMOS transistors integrated in UCL thin film SOI technology was performed. ATLAS simulations were realized and the simulations results were confirmed qualitatively by measurements over experimental UCL LDMOS. So, we are able to determine the optimal sizes of geometrical parameters such as drift and field plate lengths and also the optimal drift doping.

In conclusion, we have shown that the buried oxide thickness and physical phenomena such as kink effect and quasi-saturation impose a doping choice, which considerably reduces the breakdown voltage (about 20V) in classical LDMOS with UCL thin film SOI process. In another hand, this way of optimizing such thin film SOI devices working is a very cheap manufacturing solution on basic UCL process. To go further, new structures are under investigation.

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