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FP5

ATHIS Résumé de rapport

Project ID: G1RD-CT-2002-00729
Financé au titre de: FP5-GROWTH
Pays: United Kingdom

Limitations of IDDX methods in SoI

It has been recognised for sometime that the standard logic test methods based on “stuck-at” fault testing have had serious limitations in detecting process oriented faults which increase the “off-state” current in a circuit but do not manifest themselves as “stuck-at” faults; these types of faults ultimately affect the long term reliability of the circuit. In order to detect these faults recourse has been made to the use of current based test methods, which measure the “off-state” current, a value above the norm indicates the presence of a fault in the circuit.

However, the advances in device technology has reduced the effectiveness of this approach by raising the “off-state” fault free current to values which make the discrimination between faulty and fault free circuits difficult. Several techniques have subsequently been developed to extend the useful range of current based test methods in a background of normally high “off-state” current. These techniques can be used to good advantage in testing SoI circuits at high temperatures, the particular method being adopted is called “current ratio” method.

The only slight disadvantage of using current based testing methods with SoI circuits is that the test time will be protracted.

Success Factors:
- Understanding of test methodologies will ultimately enhance reliability.

End Users:
- Designers for microelectronic systems to be used in HT applications in automotive, aerospace, oil exploration etc.
- Manufacturers of semiconductors for HT applications.

Reported by

University of Newcastle upon Tyne
School of Electrical, Electronic & Computer Eng, Merz Court
NE1 7RU Newcastle upon Tyne
United Kingdom