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FP5

ATHIS Sintesi della relazione

Project ID: G1RD-CT-2002-00729
Finanziato nell'ambito di: FP5-GROWTH
Paese: United Kingdom

Implementation of BOST for V/I test methods

The BOST scheme, which is incorporated in the tester/oven interface, will emulate the test strategies to be used to test embedded memories in SoCs. The test stimulus is derived from programmable function blocks ensuring that the test scheme is flexible and easily modified to accommodate the changes in test algorithms for the different types of memories incorporated in SoCs, ie SRAMs, DPRAMs and EEPROMs.

The main test algorithm being used is called, generically, MARCH Test and is widely used in industry. The March test algorithm can detect all Address Faults, Stuck-at Faults, Transition Faults and Coupling Faults and has a complexity of O (10n), where n is the number of cells in the memory array. The algorithm can readily be modified to test Word Oriented Memories (WOM) by substituting the bit read/write commands in the March elements by word operations.

The March test is also combined with IDDQ test methodologies in order to detect faults in the circuits, which are elusive to voltage test methods. The particular variant of IDDQ testing used is current signatures and ed. VIs have been developed to determine the maximum value of the fault free current to be used in the current signature method.

Success Factors:
- Understanding of test methodologies will ultimately enhance reliability.
- Cost reduction in manufacture.
- Cost reduction in digital ATE and reliability test equipment.

End Users:
- Designers for microelectronic systems to be used in HT applications in automotive, aerospace, oil exploration etc.
- Manufacturers of semiconductors for HT applications.

Informazioni correlate

Contatto

Gordon RUSSELL, (Academic)
Tel.: +44-191-2227324
Fax: +44-191-2228180
E-mail