Forschungs- & Entwicklungsinformationsdienst der Gemeinschaft - CORDIS


ATHIS Berichtzusammenfassung

Project ID: G1RD-CT-2002-00729
Gefördert unter: FP5-GROWTH
Land: Spain

High temperature VDMOS power transistor

Semiconductor power devices are typically rated for operation below 150C. While digital and low power devices have been characterized at elevated temperatures, little data are available for power semiconductors over 175C. In most cases, the device is derated to zero operating power at 150-175C. We have investigated the state of the art of the high temperature commercial devices. In this sense, we found many low voltage, low on resistance MOSFET devices with an operating temperature up to 175C.

Moreover, we found another reference, the IR1704 from International Rectified, which is an HEXFET Power MOSFET that was initially expected to operate at temperatures up to 200C. However, this component has been withdrawn of the market due to unknown reasons. Consequently, we have exhaustively studied the basic cell of a MOSFET by means of numerical simulations in order to optimise the device for an operating temperature up to 200C.

This work has been focused in different ways: the identification of hot spots for different basic cell geometries, the analysis of the leakage currents with temperature, the optimisation of the device for logic level operation and finally the dynamic behaviour analysis by means of transient simulations.

Based on the simulations results, we have chosen an optimum cell pitch distance that shows the minimum peak temperature in the JFET region. Since the increase of the leakage currents is the main constrain at high temperature operation, we have also reduced the body-epitaxy junction area, since this junction is mainly responsible for the leakage current generation.

As regards the logic level operation required for the demonstrator, we have used a high dose implantation in the channel region in order to adjust the threshold voltage (around 1V) without degrading the ON-resistance values and maintaining a thick gate oxide layer to increase the reliability in the gate region.

The optimisation of the basic cell together with the optimization of the back-end processes (thick metallization, gold metal...) and package (solder alloy, substrate, coatings) allow the operation of the power device at 200C external temperature.

We have packaged different large area devices from different wafers on DCB (Direct
Copper Bonded) substrates. Specific on-resistance, threshold voltage and leakage current have been measured on package devices at 200C external temperature: the on-resistance values are in the range of 35 m¥Ø at gate voltage of 5V, the threshold voltage is 1.3V and the leakage current at 80% of the breakdown voltage is 1.2mA.

Verwandte Informationen


Miquel VELLVEHI, (Researcher)
Tel.: +34-93-5947700
Fax: +34-58-01496
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