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FP6

RESPONS Sintesi della relazione

Project ID: 40672
Finanziato nell'ambito di: FP6-MOBILITY
Paese: France

Final Activity and Management Report Summary - RESPONS (Multiple-valued applications of negative-differential resistance devices in asynchronous circuits design)

During its course, the RESPONS project had been reoriented from the development of the digital circuits technologies based on negative-differential resistance (NDR) devices, to the development of the CMOS circuit technologies employing so-called threshold logic specifically, its novel implementation called threshold logic latch (TLL). Such change was motivated by the observation that while CMOS process technology is not likely to last long below 8nm technology node, CMOS design and design automation technologies are very likely to dominate the processes that are about to appear (e.g. carbon nanotube transistor technology). Therefore the innovations should be focused on CMOS design technology.

Moving away from NDR devices was also motivated by significant shift in understanding of their potential. While at the beginning of the project the functionality of NDR-based logic circuits seemed to form a very interesting alternative to CMOS design styles, several sidelights have arisen that made us conclude that NDR devices are not and will never be applicable in the mainstream digital logic. First, the fundamental principle of operation of NDR-based logic is current-mode set-reset clocked style. With the power consumption and density being the most important constraint for current and future digital chips, current mode circuits with gate level clocking do not offer the necessary power efficiency. Second, unlike the celebrated static CMOS logic which functionally relies solely on the connectivity of the transistor network, NDR-based logic gates are essentially analogue circuits whose threshold logic operation is based on the comparison of the physical parameters of the devices. While this alone is highly susceptible to deviations in devices' parameters (process variations), the nature of the NDR devices makes the characteristics being compared highly non-linear, thus making it even more so. Consequently, current process variations levels nor their future foresights do not allow the thought that NDR-based logic gates could be manufactured and operated in the orders of billions of gates per chip. Finally, long persisting fabrication process incompatibilities give no hope to the idea of utilising NDR-based logic to augment classic CMOS logic and provide a hybrid logic style with only slight deterioration in yield yet lower power and higher performance. Therefore instead of exploring the NDR-based logic, the RESPONS project focused on exploring the potential of standard CMOS implementations of clocked threshold logic gate.

The main results produced by this project are defined by the four major cornerstones: 1) a threshold logic gate, and a characterised threshold logic standard cell library based on a novel operating principle that improves reliability of the computation, 2) a set of hybrid CMOS/threshold design techniques focused on improving circuit metrics (speed, area, power) without deteriorating its robustness, 3) a set of automatic synthesis tools that implement synthesis techniques of hybrid of CMOS/threshold circuits, 4) a technology demonstrator chip in STMicroelectronics 65nm low power technology.

The qualitative results of the project has clearly demonstrated the superiority of the proposed approach. With very little disturbance to the classic standard cell based RTL to layout design flow, we obtained a circuit technology that shows in simulations up to 35% speed improvement, or alternatively, up to 40% dynamic power reduction along with about 20% chip area reduction for a fairly complex 2-stage 32x32-bit pipelined multiplier circuit. Moreover, leakage power reduction observed reaches 2.5X what yields a promise of potential battery-life and/or performance improvements of portable devices. The fabricated demonstrator circuit confirmed the performance predicted through simulations with large margins, reaching 1.5X power reduction figures. The main results of the project has been disseminated in peer-reviewed conferences and journals.

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Laurent FESQUET
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