Wspólnotowy Serwis Informacyjny Badan i Rozwoju - CORDIS

FP6

LP_SRWC Streszczenie raportu

Project ID: 29631
Źródło dofinansowania: FP6-MOBILITY
Kraj: Ireland

Final Activity Report Summary - LP_SRWC (Low Power Short Range Wireless Communications)

The project began on 01-Feb-2006 with an expected duration of 36 months. The project originally dealt with the development of intellectual property for wireless communications - in particular the 802.15.4 and 802.11 standards for wireless communications published by the IEEE. The researchers employed for this phase of the project were primarily chosen for their expertise in the development of hardware, software and DSP solutions for wireless applications. The researchers architected and implemented innovative designs for wireless Baseband Processors and Media Access Control (MAC) layer protocols.

Although largely successful from a technical perspective, a change in Duolog's core business strategy half way through the project (Jun-2007) meant that the focus of the project had to be changed. For business reasons, Duolog abandoned its IP development activities in favour of further developing its nascent Electronic Design Automation (EDA) tool business. The original researchers' contracts were terminated and recruitment began for a new team of researchers to help with the development of EDA tools for System-on-Chip (SoC) integration. This emerging area of design automation is often called Electronic System Level (ESL) design.

By the end of the project, a team of 8 researchers had been recruited to work with Duolog's R&D teams to develop the "Socrates" suite of EDA tools. The Socrates tools tackle a growing problem in the chip design industry - how to correctly assemble and interconnect the many complex IP blocks that make up a modern SoC. In particular, the researchers were instrumental is developing the following products:
Socrates Bitwise: This tool is used to specify the hardware/software interface of an IP, sub-system or full system. Software communicates with hardware via "registers" and "memories". These elements are fully specified in Bitwise and the tool then generates all necessary hardware, software and verification code and documentation relating to these elements.
Socrates Spinner: This tool specifies the I/O layer of a chip - all of the functionality lying between the core functional area of the chip and the package pins. As chips become larger and more configurable, this layer is becoming increasingly complex and error-prone. Spinner auto-generates the full design of the I/O layer, eliminating potential errors.
Socrates Weaver: In order to automate the interconnections between IP blocks, it is first necessary to "package" the IP interfaces in such a way that connections can be inferred. Weaver performs this packaging, and then automates the block interconnections via a connection rule-set. The first customer release of Weaver is expected in July, 2009.

The Socrates tools fully support the IP-XACT standard for IP packaging. All of the Socrates tools run on the popular "Eclipse" Integrated Design Environment (IDE) and therefore run on all major platforms (Windows, Linux, Solaris). The innovative approach taken by the researchers and their colleagues in Duolog's R&D teams in the development of Socrates has quickly made Duolog the leading player in this emerging segment of the EDA/ESL market.

Kontakt

Michelle LYNCH, (Wireless DSP Group Leader)
Tel.: +353-91-730832
Faks: +353-91-730821
Adres e-mail
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