Final Report Summary - CALDERA (Clustered Atomic Layer Deposition for Emerging micRoelectonic Applications) A lesser known aspect of Moore's law is the need for increased performance (performance scaling), notably with an increase in the drive current Ion of the transistors. Since Ion is proportional to Cox.µ/L (Cox = gate capacitance, µ = carrier mobility, L = channel length), dimensional scaling by reducing L and increasing Cox by decreasing the gate dielectric thickness led to increased transistor performance. However, gate leakage currents started to dominate for L = 135 nm and below, which led to the need for new high-K materials as gate dielectrics. In addition to dimensional scaling, recent work to improve Ion is increasingly based on alternative materials with higher electron mobility µ, thereby replacing silicon as the channel material. The most promising high-µ materials are III-V compound semiconductors such as GaAs, InGaAs, or InP.[1] One of the biggest challenges for integrating III-V semiconductor into Si CMOS technology is the passivation of the interface between the channel and the gate dielectric, known for decades in the III-V world as surface Fermi level pinning (FLP). According to the current understanding, defects such as dangling bonds, vacancies and interstitials at or near the interface give rise to additional energy states in the band gap, leading to FLP and degraded device performance. Such defects may be created at the III-V surface during the formation of native oxides, e.g. in air or in wet cleaning solutions. It is thus important to either remove these defects or avoid their formation before the deposition of the gate dielectric. The issue of FLP at III-V-dielectric interfaces has led much work on various means of depositing gate dielectrics after removing the native oxides from III-V surfaces. The identification of a viable passivation layer, which avoids the formation of defects during air exposure or during the deposition process, has also been sought. Numerous wet wafer cleaning processes have been tried and found indeed to partially remove the native oxides but were not sufficient for device fabrication.[2] Buffer layers of various sorts have been placed at the interface, with the most prominent to date being Ga2O-based.[3] However, these Ga2O-based buffer layers were only successful when grown by molecular-beam epitaxy (MBE) on GaAs surfaces in a cluster tool, which allows deposition of Ga2O without previously having an air break after GaAs deposition. While leading to a good passivation of the GaAs surface, the drawback of this method is that it leads to a rather modest dielectric quality of the gate stack. Furthermore it cannot provide the throughput required for practical mass-production of semiconductor devices. The most promising of gate dielectrics suitable for the practical manufacture of III-V semiconductors which has been found so far is aluminium oxide when grown by atomic layer deposition (ALD) from trimethyl aluminium (TMA) and water.[4] ALD is already a well commercialised process which has been incorporated into the current production of semiconductor devices, as contrasted with MBE. The ALD process[5] is a thin film deposition technique akin to chemical vapour deposition (CVD) but yielding superior control and conformality of the film growth. The power of the ALD process stems from the use of alternating pulses of two complimentary gas-phase sources; which are reactive towards each other, inert towards themselves and together provide all the components of the desired thin film. By repeatedly applying these two reactants sequentially in separated pulses, the reaction is limited to the molecules bound to the surface. This removes the possibility of side-reactions, which would cause uncontrolled growth, and thus provides excellent conformality and step coverage. A further advantage of ALD processes is the lower process temperature of typically 300 °C as compared to the temperatures of approximately 500 °C or higher typically found in CVD or MBE processes. These lower process temperatures apply less stress to the substrates, help reducing overall thermal budgets and reduce the parasitic oxidation of the interface during the high-K oxide growth, which is especially relevant for III-V materials, particularly in view of their much lower thermal stability with respect to Si. The ALD of aluminium oxide has been found to be especially successful since the native III-V oxide is consumed during the initial growth of the aluminium oxide layer due to the specific reactions occurring during the ALD process.[6] However, although ALD aluminium oxide can provide excellent native-oxide-free interfaces with the III-V semiconductors, the interface defect density is much larger than that of SiO2/Si interfaces and further improvements are necessary. The underlying root cause for the high defect density may stem from the oxidization process of III-V surface, which may not only lead to defects at the interface between the native oxide and the bulk of the material but also to sub-interface defects, which remain in the bulk of the film even when the surface oxide is removed.[3, 7]Whereas ex-situ measurements have been very useful in Si and Ge based materials systems, the higher reactivity and more complex reaction mechanisms of III-V surfaces with the ambient atmosphere necessitate in situ analysis, without exposure to the outside air. Thus, in situ analysis tools in combination with a clustered deposition tool provide an ideal means to study the initial stages of ALD on III-V surfaces and the interface formation since all air exposure between film growths and measurements will be avoided. By enabling exactly such a combination, this project will provide the clearest insight into the growth mechanisms of ALD and of III-V interfaces to date. Previous in situ analysis during ALD growth has been done with Fourier transform infra-red (FT-IR) [8], X-ray photoelectron spectroscopy (XPS)[8], residual gas analysers (RGA) [9] or scanning tunnelling microscopy (STM) [10], but never with a combination of analysis tools. Since they provide complimentary information, all are not only needed but must also be applied to the same sample for the most meaningful results. This work focused on InP by combining STM, scanning tunnelling spectroscopy (STS) and synchrotron XPS, all performed in-situ. Two different cleaning procedures were considered, one terminating with an ammonium sulphide etch and the other ending with a sulphuric acid etch. The STM images of the ammonium sulphide cleaned InP were found to present a rough surface with a measured RMS roughness value of 0.28 nm. After sulphuric acid etching, the surfaces were covered with smooth terraces. The terrace height was measured at half of the unit cell length, which corresponds to one repeat of In-P per step. The RMS roughness was 0.21 nm and the terrace width was dependent on etching conditions. After ammonium sulphide cleaning, the phosphorus 2p peak showed a reduction in the P5+ peak relative to the native oxide along with the presence of some sub-oxides. After sulphuric acid cleaning there also remained some P3+and P0. The overall removal of oxides was less in the case of sulphuric acid, with approximately 4.5 Å as compared to 2 Å left after ammonium sulphide etching. The indium 3d peak showed the presence of In3+ and In0 in addition to InP. The sulphuric acid clean showed a greater fraction of In3+ on the surface. The P5+ peaks were assigned to an indium phosphate in the native oxide and to a hydrogenated phosphate in the etched samples due to the slight peak shift after etching. Due to the smoother surfaces, the sulphuric acid etched samples were selected for the growth studies despite having somewhat worse electrical performance when characterised by capacitance - voltage measurements in prior studies. Samples were studied by STM after an exposure to TMA and also after two, five and ten cycles of ALD with TMA and water. Analysis of a growth series by ICP-AES showed linear growth through the region of 1 to 30 ALD cycles measured on InP. The number density of islands was found to be 0.05/nm2 and remained constant throughout the increasing numbers of ALD cycles. The measured height of the islands after the first pulse was 5 Å and the diameter was measured at 3.7 Å. This yields an average film growth of 3 Å for the first cycle, as compared to a growth rate of 1 Å /cycle more typically found for TMA and water. This enhanced growth in the first few cycles of ALD was also noted in the areas of the aluminium peaks in XPS. Film closure was seen at 10 cycles, which corresponds to a growth of 1 nm of film. After TMA exposure, the P5+ peak shifts to higher binding energy which is assigned to the formation of AlPO4. Subsequent cycles of TMA and water did not lead to changes in the phosphorus spectra. A decrease in the In3+ fraction was also seen after TMA exposure which was also unchanged after the following cycles. Whether this decrease is due to a formal reduction of the In3+ or the formation of volatile trimethylindium by the transfer of methyl ligands from TMA is unclear. Analysis of the start of the valence band showed a negligible shift after TMA exposures showing the Fermi level is still pinned with a defect density of at least 1E12 cm-2. Selected sample density of state curves showed a wide band gap with several mid-gap states present. The average value of the bandgap was 2.5 ± 0.3 V for the ammonium sulphide cleaned and 5.0 ± 0.9 V for the sulphuric acid cleaned. This reduced to 3.1 ± 0.5 V after exposure to TMA and gradually increased to 5.3 ± 0.5 V after ten cycles. The bandgap of over 5 V, uncorrected for tip effects, is consistent with the wide band gaps expected for the phosphate surface oxide. The primary cause of the increased bandgap was seen to be a decrease in the valence band edge voltage, which is ascribed to oxidation of the surface. The spatial variation of the measured band edges was apparently random, with no correspondence with the observed surface features. Variations were also highly localized in a pinhole-like manner.Thus, the generation of defects on the InP surface has been found to be associated with oxidation of the surface and that current surface cleaning methods and gate stacks are inadequate for the complete removal of these defects. Therefore the economic manufacture of InP devices for high-performance computing will require the avoidance of any possible oxidation, including that by ambient air, throughout the creation of the InP channels and the complete fabrication of the device. 1. Heyns, M. et al., MRS Bulletin, 2009, 34, 485; DUALLOGIC, European Commission (EC) Seventh Framework Programme (FP70 project No. 2145792. Caymax, M. et al., Microelectronic Engineering, 2009, 86, 1529.3. Passlack, M. et al., Appl. Phys. Lett., 2004, 84, 2521; Holland, M. et al., Microelectronic Engineering, 2009, 86, 244.4. Hinkle, C. L. et al., Appl. Phys. Lett., 2008, 92, 071901; Sioncke, S. et al., J. Electrochem. Soc., 2009, 156, H255.5. Puurunen, R. L., J. Appl. Phys., 2005, 97, 121301.6. Wallace, R. M. et al., MRS Bulletin, 2009, 34, 493.7. Spicer, W. E. et al., J. Vac. Sci. Technol., 1980, 17, 1019; Spicer, W. E. et al., J. Vac. Sci. Tecnol. B, 1988, 6, 1245.8. Frank, M. M. et al., Appl. Phys. Lett., 2003, 82, 4758.9. Rahtu, A. et al., Langmuir, 2001, 17, 6506.10. Shin, B. et al., Appl. Phys. Lett., 2010, 96, 252907.
