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Content archived on 2024-04-15

Advanced Algorithms, Architecture and Layout Techniques for VLSI Dedicated Signal-Processing Chips


The objectives were to produce:
-A set of methods, algorithms and CAD tools for the design of digital signal processing chips in state-of-the-art CMOS technology using new advanced optimised circuit techniques and clocking schemes.
-Tools to support formal as well as interactive design from specifications down to chip layout. The CAD tools so produced should be capable of optimising chip area and power dissipation for given system requirements.
Design methodologies and the appropriate design tools for several specific digital signal processing architectures have been developed. These architectures are:
A.Bit-Serial architecture
B.Cooperating Datapath architecture: restricted to linear pipelined bit-parallel hardwired structures within the project
C.Pipelined Regular Array structures: restricted to systolic or semi-systolic arrays within the project
D.Micro-coded Multi-Processor structures.
The objectives were to produce:
a set of methods, algorithms and computer aided design (CAD) tools for the design of digital signal processing chips in state of the art complementary metal oxide semiconductor (CMOS) technology using new advanced optimised circuit techniques and clocking schemes;
tools to support formal as well as interactive design from specifications down to chip layout.

Design methodologies and the appropriate design tools for several specific digital signal processing architectures have been developed. These architectures are:
bit serial architecture;
cooperating datapath architecture (restricted to linear pipelined bit parallel hardwired structures);
pipelined regular array structures (restricted to systolic or semisystolic arrays);
micro coded multiprocessor structures.
The operating environment is as follows :
Computer aided design (CAD) and design methodologies
The work on the hardwired bit-serial architecture has resulted in a complete set of integrated tools to specify a filter, synthesise it in a wave digital form, simulate it on different levels, optimise the coefficients and the data-wordlengths, map the algorithm - including the control - into the bit-serial primitives and generate the complete layout.
A study of design methods for two-dimensional wave digital filters with approximately circular symmetry has been made. Besides the design of two-dimensional cross-antimetric filters, a new method has been worked out, which can be extended to any number ofdimensions. Several structures for two-dimensional antimetric filters have been developed with a high degree of modularity.
The whole integrated CAD package, which is a fully operational silicon compiler from specifications to layout,is called CATHEDRAL-I.
B.Cooperating Datapath
A novel carry-save technique and special circuit cells for overflow protection have been studied and documented with the intention of achieving a 100 MHz clocking rate in a modern CMOS technology. This is very important in order to achieve the performanceaimed at, for example, in the RACE programme, with more traditional and therefore cheaper technologies than GaAs. The set of software tools that has been developed is embedded in the CATHEDRAL-III environment.
C.Regular Array
A standard module library which can be used to span most of the arithmetic-intensive operations in the area of image processing has been derived, and a composition methodology has been studied which can later be translated in a set of synthesis tools for regular array structures (not part of this project).
Self-test approaches for the concurrent sorting architecture have been investigated. A fault coverage of 100% for stuck-at and up to 99.6% for stuck-open faults have been obtained for a bit-serial word sorter. Two word-parallel bit-serial sorting networkshave been implemented using MGE. The circuits occupy areas of 13.6 mm2 and 36.6 mm2 respectively.
The main emphasis was placed on this type of architecture. It is most suited for a large majority of applications in the spectrum up to 1 MHz sample rate and it addresses the implementation of more general real-time algorithms. The design methodology for this architecture has been derived from four large applications in speech processing and telecommunications.
This work resulted in a true silicon compiler, CATHEDRAL-II. It translates a behavioural, flowgraph-type algorithm description, expressed in the SILAGE language, into a dedicated multi-processor architecture. It allows the system designer to investigate and compare in an interactive way a number of silicon implementations of a certain digital signal processing algorithm.
The datapath of the chip is constructed from a customised set of parameterisable execution units. This customised datapath is generated automatically from the high-level behavioural specification. The set of available execution units is restricted to six:ALU/shift, Address Computation Unit, multiplier/accumulator, comparator, normaliser, RAM/FIFO. A study has been made on the interprocessor communication protocols, addressing techniques and bus interconnection strategy. The results have been embedded ina software tool outside the scope of the project (IMEC).
Although the first CATHEDRAL-II prototype showed very promising results, the different exercises that have been done have shown that the inference mechanism, as implemented, was not efficient enough for larger examples and missed the robustness to handle complicated nestings of loops and conditionals. A new inference mechanism was therefore implemented, based on demand-driven rule firing, by which a higher efficiency is reached for much more complex examples (IMEC).
CATHEDRAL-I has already been installed at different universities, research institutes and companies throughout the world. Besides installation at the partner sites, the software is also used at, amongst others, Italtel, RCA, University of California (Berkeley, USA), University of Lund (Sweden), Institut de Microtechnique de l'Universit de Neuchtel (Switzerland), University of So Paulo (Brazil), etc.
The CAD system has been successfully applied to the design of a viewdata filter (Philips, IMEC) and to the design of a PCM-FDM Transmultiplexer with a complexity of 35 000 transistors (Siemens, IMEC).
B.Cooperating Datapath
CATHEDRAL-III is oriented to the efficient synthesis of high-throughput digital signal processing circuits in which the clock rate/sample rate ratios vary between one and twenty.
A bit-parallel digital transversal filter, with real-time programmable coefficients, has been designed in a 1.5 micron CMOS technology. It has been measured and verified for a clock rate of up to 50 MHz. A third-order wave digital filter has been designedby Siemens, and implemented on chip. The total chip area is 14.7 mm2 (in a 2 micron CMOS technology) and the maximum measured clock rate is 50 MHz.
Other demonstrators are the integration of a Cordic algorithm and a digital video signal convertor (RGB to luminance/chrominance) with decimation filters (DMF). This last application will be used in a 140 Mbit/s video codec in order to replace analogue circuitry. The design is suitable for implementation with a 1.5 micron CMOS technology, yielding a chip with about 80 000 transistors on a total chip area of about 35 mm2 (Siemens, IMEC).
C.Regular Array
At IMEC, architectures for the distance computation unit in a video codec have been investigated in cooperation with Alcatel/Bell Telephone. In addition, several efficient semi-systolic architectures for one-dimensional and two-dimensional running order statistics filters have been developed.
Different instances of almost all required execution units have been put on MPC in a 3 micron and a 2.4 micron double-metal CMOS technology and tested successfully. This has been done partly outside the scope of project (by IMEC). A 1.6 micron version hasbeen developed by Philips, also outside the scope of the project.
From this, a powerful microcode ROM based multi-branch controller architecture has been selected (IMEC, Philips), though other architectures such as a simple FSM can also be incorporated. Alcatel/Bell has studied one particular controller architecture, the binary decision machine, and has translated this into a set of specifications for dynamic ROM and RAM structures.
The CATHEDRAL-II version, as delivered at the end of the project, has proven its usefulness in different applications. Within Philips, CATHEDRAL-II has been used in order to build PIRAMID, an operational silicon compiler fitted to Philips' requirements. Different designs have been completed. CATHEDRAL-II and PIRAMID are being used intensively within IMEC, Philips and Alcatel/Bell Telephone.
EDC (European Development Centre), a research and development organisation located in Leuven, Belgium, jointly owned by Mentor Graphics, Philips International BV and IMEC, is using and commercialising the major results of the project. The resulting products and technologies will be distributed by Mentor Graphics as part of their Falcon Framework.


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