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Integrated Circuit Design for Signal Processing

Exploitable results

Research for circuit design for signal processing was pursued in 2 areas: in order to overcome synchronization problems on the chip, asynchronous circuit concepts were discussed in detail and test vehicles implemented; complementary metal oxide semiconductor (CMOS) versus BCMOS was studied realizing various macro building blocks. Concerning the design of asynchronous circuits, low level circuit design and building blocks in micropipeline architecture were studied. Improvements have been achieved in the design of handshake circuitry. Major properties of the developed circuits are relaxed timing constraints and therefore improved reliability. Some efforts were made to apply design automation techniques (ie standard cell methodology) to the design of asynchronous circuits. This led to the development of a standard cell library consisting of DCVSL functional cells and handshake circuitry, respectively. The well known scan path technique was introduced to assure for testability. Appropriate cells were designed and added to the library to allow for the implementation of scan paths together with self timed modules and building blocks. 2 self timed test circuits, a serial parallel multiplier and a Booth multiplier with scan path were designed and successfully tested. Novel BICMOS circuit concepts for interchip communication tunable filters and for a logic level converter ECL to CMOS have been developed. Prototypes and test results are available.