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Ultra-Low PoweR technologIes and MEmory architectures for IoT

Objetivo

The goal of the PRIME project is to establish an open Ultra Low Power (ULP) Technology Platform containing all necessary design and architecture blocks and components which could enable the European industry to increase and strengthen their competitive and leading eco-system and benefit from market opportunities created by the Internet of Things (IoT) revolution.
Over 3 years the project will develop and demonstrate the key building blocks of IoT ULP systems driven by the applications in the medical, agricultural, domestics and security domains. This will include development of high performance, energy efficient and cost effective technology platform, flexible design ecosystem (including IP and design flow), changes in architectural and power management to reduced energy consumption, security blocks based on PUF and finally the System of Chip and System in Package memory banks and processing implementations for IoT sensor node systems.
Developped advanced as 22nm FDSOI low power technologies with logic, analog, RF and embedded new memory components (STT RAM and RRAM) together with innovative design and system architecture solutions will be used to build macros and demonstrate functionality and power reduction advantage of the new IoT device components.
The PRIME project will realize several demonstrators of IoT system building blocks to show the proposed low power wireless solutions, functionality and performance of delivered design and technology blocks.
The consortium semiconductor ecosystem (IDMs, design houses, R&D, tools & wafer suppliers, foundries, system/product providers) covers complementarily all desired areas of expertise to achieve the project goals.
The project will enable an increase in Europe’s innovation capability in the area of ULP Technology, design and applications, creation of a competitive European eco-system and help to identify market leadership opportunities in security, mobility, healthcare and smart cost competitive manufacturing.

Convocatoria de propuestas

H2020-ECSEL-2015-1-RIA-two-stage-Master

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Convocatoria de subcontratación

H2020-ECSEL-2015-1-RIA-two-stage

Coordinador

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Aportación neta de la UEn
€ 3 116 585,00
Dirección
KAPELDREEF 75
3001 Leuven
Bélgica

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Región
Vlaams Gewest Prov. Vlaams-Brabant Arr. Leuven
Tipo de actividad
Research Organisations
Enlaces
Coste total
€ 7 791 462,50

Participantes (16)