The objective of the OMI/HIC project is to provide low-cost, high-performance serial interconnect for the OMI. It will develop technologies to provide a range of cost/performance tradeoffs within a common protocol framework, at moderate distance scales, ie chip-to-chip, board-to-board, rack-to-rack and room-to-room. Target performance levels are 200 Mbaud, 700 Mbaud to 1 Gbaud, and 2-3 Gbaud.
The design of a higher speed digital signal (DS) link is nearly complete. Prototype complementary metal oxide semiconductor (CMOS) driver and receiver circuits for optical interconnect are being tested. A CMOS chip has been developed to provide a parallel interface to a 1 Gbaud serial link, with built in support for the lower levels of the protocol stack. A test chip has demonstrated feasibility of 3 GBaud in a bipolar CMOS (BiCMOS) device. A design study for a high-performance routing chip with advanced features has been done. A book has been published about DS-Links and their applications, and the protocols developed within the project are the basis for a draft IEEE standard, p1355.
The project aims to:
- double the performance of INMOS DS-Links to 200 Mbaud, and provide drivers/receivers for fibre optic interconnect at these speeds (using an encoding developed in the GPMIMD project)
- develop 1 Gbaud serial link technology, implemented in 0.5 micron CMOS, with protocols conforming to the OMI high-level interconnect standard
- evaluate BiCMOS as a technology for 2-3 Gbaud serial links on copper media and provide drivers/receivers for fibre optic interconnect at 1 Gbaud
- provide macrocells supporting the serial link technologies to the ELI library standards
- develop routing and interfacing chips based on serial link technology
- demonstrate use of the serial links on at least two different processor architectures
- demonstrate use of the serial links as a transport mechanism for SCI (IEEE 1596) protocols.
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20010 Pregnana Milanese Milano
92039 Paris La Défense
92045 Paris La Défense