Objective
The objective of this project is to develop a methodology for functional test generation in microelectronics. Testing and diagnosis have great problems in managing the complexity of a system design. One promising way to overcome these problems would involve functional aspects at the system level rather than structural ones at the gate level only. Then it will become possible for system level VHDL descriptions to be the basis for the generation of tests for validation and fault diagnosis.
Three different approaches will be pursued:
Test generation and fault simulation in digital circuits and systems using a new concept based on alternative graphs
Generation of test patterns for VHDL descriptions of VLSI circuits, with test patterns derived from expressions evaluated by symbolic simulation
Generation of test patterns at the algorithmic level.
These activities are accompanied by investigations into developing a method for optimal ordering of fault simulation techniques, a methodology for automating the test scheduling process, and application of artificial intelligence to functional test generation.
European links:
One of the partners is involved in ESPRIT Project 6575 (ATSEC).
Topic(s)
Data not availableCall for proposal
Data not availableFunding Scheme
CSC - Cost-sharing contractsCoordinator
01069 Dresden
Germany