Objective Recent research has led to the discovery that crystals, 50 to 500 nm in size and with a regular geometric structure, can be coated with nano-particles of size 4 to 16 nm. At present, the coating is metallic, and the crystal core is insulating, but it is believed that cores and coatings can be made which are insulating, conducting or semi-conducting. It is anticipated that different types of units can be made, and that it will be possible to self-assemble different units to produce memory elements, transistors or other components in extremely large numbers, and to align these in larger arrays. The proposed ESCHER project will investigate the chemical preparation of different types of "building blocks", the electronic and structural properties of individual units, and the self-assembly of different units to make large numbers of active electronic components. Recent research has led to the discovery that crystals, 50 to 500 nm in size and with a regular geometric structure, can be coated with nano-particles of size 4 to 16 nm. At present, the coating is metallic, and the crystal core is insulating, but it is believed that cores and coatings can be made which are insulating, conducting or semi-conducting. It is anticipated that different types of units can be made, and that it will be possible to self-assemble different units to produce memory elements, transistors or other components in extremely large numbers, and to align these in larger arrays. The proposed ESCHER project will investigate the chemical preparation of different types of "building blocks", the electronic and structural properties of individual units, and the self-assembly of different units to make large numbers of active electronic components.OBJECTIVESThe long-term objective is to develop self-assembly techniques for making nano-electronic computing structures. The specific objectives are to investigate the self-assembly of nano-crystals with a uniform coating of nano-particles, to measure their electronic properties, and to examine the further self-assembly of these "blocks" into active electronic devices.The technical objectives are:1. chemical preparation of a variety of nanoscale building blocks;2. development of techniques for producing uniform-sized blocks;3. structural and electronic measurements (using STM, SEM, TEM etc.);4. demonstration of alignment of one type of block on a metallic grid;5. demonstration of self-assembly.DESCRIPTION OF WORKWe propose a three-year program to examine a new method of self-assembly for nano- electronic components and its potential application in producing computing devices and systems.The self-assembly process is realised at several levels, which are described in detail in the proposal. The basic "building block" is a geometrically regular crystal core (e.g. a "block" of typical size 50X100x30nm, but larger or smaller as required), coated with a layer of nano-particles (5 to 15 nm thick). The core and the coating may be insulating, semi-conducting or conducting. The project will involve a progressive investigation and development of increasingly complex self-assembled structures, using these basic building blocks. These structures will include transistors and memory elements.There will be five work packages(WP):WP1 - BUILDING BLOCKS: synthesis and deposition of a variety of building blocks (different combinations of the core crystal and coating material) and analysis of the shape, size distribution, and techniques to control these features. Two types of block will be developed, the first (type 1) having an insulating core and metallic/semiconducting outer layer, the second (type 2) having a metallic or semiconducting inner layer and insulating coating;WP2 - STM and conductivity scans (etc) of single units;WP3 - SINGLE UNIT SELF-ALIGNMENT: Deposition and self-alignment of type-1 (type-2) blocks on a prefabricated metallic grid, analysis of uniformity and coverage, measurement of electrical properties of individual or multiple blocks;WP4 - MULTIPLE UNIT SELF-ASSEMBLY: Deposition and self-assembly of combinations type- 1 and 2 blocks on metallic tracks, and measurement of electrical properties;WP5 - THEORETICAL PERFORMANCE ASSESSMENT: Theoretical modelling of electronic properties etc of individual blocks and combinations of blocks. Fields of science engineering and technologynanotechnologynano-materialsnanocrystalsengineering and technologymaterials engineeringcoating and films Keywords Nanotechnology Programme(s) FP5-IST - Programme for research, technological development and demonstration on a "User-friendly information society, 1998-2002" Topic(s) IST-2001-6.2.1 - Nanotechnology information devices Call for proposal Data not available Funding Scheme CSC - Cost-sharing contracts Coordinator UNIVERSITY COLLEGE LONDON EU contribution No data Address GOWER STREET WC1E 6BT LONDON United Kingdom See on map Total cost No data Participants (3) Sort alphabetically Sort by EU Contribution Expand all Collapse all GERHARD-MERCATOR-UNIVERSITAET GESAMTHOCHSCHULE DUISBURG Germany EU contribution No data Address LOTHARSTRASSE 65 47048 DUISBURG See on map Total cost No data NATIONAL CENTRE FOR SCIENTIFIC RESEARCH "DEMOKRITOS" Greece EU contribution No data Address 15310 AGHIA PARASKEVI ATTIKIS See on map Total cost No data UNIVERSITY OF STRATHCLYDE United Kingdom EU contribution No data Address RICHMOND STREET 16 G1 1XQ GLASGOW See on map Total cost No data