Objective
ADOC puts together reusable innovative ASIC ?ores that go beyond the state of the art for OFDM-based Communications. The cores will be used in a family of integrated circuits that are based on the state-of-the art OFDM technology, including chipsets for high-speed Powerline Acces modems, high-speed Powerline LAN cards, VDSL and Wireless Local Loop. The library of cores will be integrated in the design flow so that the productivity of the design teams is highly increased. Once the prototypes have been finished and validated in laboratory test, they will be evaluated at different 'real-life' scenarios in order to determine the fulfilment of the specified requirements. In order to develop a channel model suitable for the IP Cores development, the Channel characterization of the Medium Voltage lines will take place. High- speed transmission through the MV network will enable a very cost effective deployment of technology.
OBJECTIVES
The technological objectives of the proposal are the development, test, validation and documentation of following reusable ASIC Cores that go beyond the state of the art, as justified in Part B of this proposal: - 2048-carriers OFDM- Point to Multipoint Core- Power Line Bridge - 802.1d MAC Bridge - USB Full Speed Physical Transceiver- 80 Msps 10 bits DA Converter- 80 Msps 10 bits AD Converter- High Frequency Lineal Bandpass analogue filters- Low Noise Amplifier - Ultra-low distortion Programmable Gain Amplifier- High-current/low-distortion Line Driver.
DESCRIPTION OF WORK
The project starts with a requirements definition, going from the market requirements, through the system specification, to the specific core requirements. At this stage, the medium voltage (MV) network has to be studied and characterized in-depth in order to be able to develop a channel model suitable for the ASIC development and to acquire the knowledge around the transmission media that will optimize the technology developments. The digital cores will be written in Verilog HDL following special coding guidelines for readability and easy comprehension of functionality. After that, exhaustive regression tests will be written for all blocks. Also a test bench for the complete design will be written and applied to the complete design. This will scope the parameterizability of the blocks, and will test all the possible parameters combinations. For the OFDM core, the regression test will use the already available C simulation tools to guarantee the right functionality. These C tools allow a co-design and co-verification between Verilog HDL and C simulation of the whole system. For the analogue cores, the circuit architecture best suited for the specified requirements has to be researched and selected, through compression and simulation with SPICE like tools. Process tolerances have to be considered to ensure robustness against technology dispersion. Next step is the layout that is performed taking into account specific design techniques to assure a good component matching, at least between critical components in the design, and layout simulation after parasitics extraction. ASIC samples will be verified in the lab and deviations against the required parameters will be identified and corrective actions in the design established. The final validation of the cores against the initial requirements will be accomplished through a field trial. Once the cores have been validated, the customer documentation needed for a third party to reuse the developed core will be prepared.
Fields of science (EuroSciVoc)
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CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
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Call for proposal
Data not availableFunding Scheme
CSC - Cost-sharing contractsCoordinator
12002 CASTELLO
Spain