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Multi-coRe, multi-level, WDM-enAbled embedded optical enGine for Terabit board-to-board and rack-to-rack parallel optics

Multi-coRe, multi-level, WDM-enAbled embedded optical enGine for Terabit board-to-board and rack-to-rack parallel optics

Objective

MIRAGE aims to implement cost-optimized components for terabit optical interconnects introducing new multiplexing concepts through the development of a flexible, future-proof 3D "optical engine".
Data centers are becoming the hot spots of internet, and content providers request a technology for practical and cost-effective upgrade to Tb/s capacities. MIRAGE is an industry-driven photonic integration project that aims to provide this technology and present a viable path to scale datarate (+640%), power (-70%) and no. of fibres (-90%) by squeezing bulk parallel optical components into 3D integrated chips. MIRAGE will introduce new dimensions of parallelization in interconnects to gracefully upgrade capacity and density combining for the first time multi-core fiber multiplexing, coarse WDM multiplexing and multi-level modulation. To address cost, performance and volume MIRAGE relies on the strengths of Si photonics and electronics and extends it using the right synergies with established photonic integration materials (InP and glass) to provide a future-proof, upgradeable technology. MIRAGE optical board will provide efficient (2dB) vertical coupling for photonic 3D integration and compact wavelength multiplexing on 8” Si wafers. MIRAGE will exploit the efficiency of VCSEL technology to develop the first SOI-compatible 40Gb/s InP VCSELs at 1550nm and will upgrade them to 80Gb/s through simple multi-level modulation. To further address parallelization, MIRAGE will integrate the InP VCSELs in monolithic WDM arrays. Leveraging advances in single-mode multicore fiber MIRAGE aims to mitigate cabling cost and size and reduce chip area for pigtailing by developing low-cost glass multi-core interfaces with simple assembly on the SOI chip. 4-element silicon TIA and VCSEL driver arrays will be implemented for 40 Gbaud multi-level modulation. Low-cost industry-compatible 3D assembly techniques will be optimized for high-speed electro-optic chips, bringing a >50-fold improvement in electrical vias capacitance. MIRAGE will deliver fully functional 3D PICs: a) 208 Gb/s board-level interconnect b) 320 Gb/s QSFP active optical cable (AOC) c) 960 Gb/s CXP AOC with QSFP breakout.
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Coordinator

INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS

Address

Patission Str. 42
10682 Athina

Greece

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 447 398

Administrative Contact

Hercules Avramopoulos (Prof.)

Participants (7)

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AMS AG

Austria

EU Contribution

€ 380 189

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

Belgium

EU Contribution

€ 639 322

GESELLSCHAFT FUR ANGEWANDTE MIKRO UND OPTOELEKTRONIK MIT BESCHRANKTERHAFTUNG AMO GMBH

Germany

EU Contribution

€ 284 118

TECHNISCHE UNIVERSITAET MUENCHEN

Germany

EU Contribution

€ 480 439

ARISTOTELIO PANEPISTIMIO THESSALONIKIS

Greece

EU Contribution

€ 323 260

MELLANOX TECHNOLOGIES LTD - MLNX

Israel

EU Contribution

€ 267 180

OPTOSCRIBE LIMITED

United Kingdom

EU Contribution

€ 178 058

Project information

Grant agreement ID: 318228

Status

Closed project

  • Start date

    1 October 2012

  • End date

    31 May 2016

Funded under:

FP7-ICT

  • Overall budget:

    € 4 314 208

  • EU contribution

    € 2 999 964

Coordinated by:

INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS

Greece