"Computer architects are facing two critical challenges when designing parallel architectures - making them both dramatically more power efficient and far more easy to program. These challenges, often referred to as the power and programmability walls, already bring forth two orthogonal paradigm shifts in parallel programming and computer architecture.
On the one hand, the parallel programming world is turning towards task-based parallel programming models, which direct programmers to decompose their program into computational tasks that can execute in an asynchronous manner. On the other hand, power limitations and inefficiencies inherent to von-Neumann architectures motivate the exploration of novel programmable accelerators.
In this research, whose focus stems from the culmination of the above trends, we will focus on the exploration and design of high-performance, power-efficient compute fabric that is tuned to efficient execution of encapsulated computational tasks. To achieve high-performance as well as power efficiency, the fabric will be based the dataflow computing model, which potentially offers great power and performance potential over traditional von-Neumann architectures.
The research will focus on the development of a novel single-graph multiple-flows (SGMF) reconfigurable accelerator model that combines task-level parallelism with power-efficient data graph execution. The SGMF model identifies multiple instances of a computational task type and maps their shared data graph representation onto a grid of simple functional units. The grid then concurrently streams multiple data graph instances thus executes tasks in parallel. SGMF therefore offers a general-purpose, power-efficient dataflow alternative for the increasingly popular single-instruction multiple-thread (SIMT) model."
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