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Mont-Blanc 2, European scalable and power efficient HPC platform based on\nlow-power embedded technology

Objective

The Mont-Blanc project aims to develop a European Exascale approach leveraging on commodity power-efficient embedded technologies. The project has developed a HPC system software stack on ARM, and will deploy the first integrated ARM-based HPC prototype by 2014, and is also working on a set of 11 scientific applications to be ported and tuned to the prototype system.
The rapid progress of Mont-Blanc towards defining a scalable power efficient Exascale platform has revealed a number of challenges and opportunities to broaden the scope of investigations and developments. Particularly, the growing interest of the HPC community in accessing the Mont-Blanc platform calls for increased efforts to setup a production-ready environment.
The Mont-Blanc 2 proposal has 4 objectives:1. To complement the effort on the Mont-Blanc system software stack, with emphasis on programmer tools (debugger, performance analysis), system resiliency (from applications to architecture support), and ARM 64-bit support2. To produce a first definition of the Mont-Blanc Exascale architecture, exploring different alternatives for the compute node (from low-power mobile sockets to special-purpose high-end ARM chips), and its implications on the rest of the system3. To track the evolution of ARM-based systems, deploying small cluster systems to test new processors that were not available for the original Mont-Blanc prototype (both mobile processors and ARM server chips)4. To provide continued support for the Mont-Blanc consortium, namely operations of the Mont-Blanc prototype, and hands-on support for our application developers
Mont-Blanc 2 contributes to the development of extreme scale energy-efficient platforms, with potential for Exascale computing, addressing the challenges of massive parallelism, heterogeneous computing, and resiliency. Mont-Blanc 2 has great potential to create new market opportunities for successful EU technology, by placing embedded architectures in servers and HPC.
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Coordinator

BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION

Address

Calle Jordi Girona 31
08034 Barcelona

Spain

Activity type

Research Organisations

EU Contribution

€ 1 808 660

Administrative Contact

GUADALUPE Moreno (Ms.)

Participants (17)

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UNIVERSITAET STUTTGART

Germany

EU Contribution

€ 368 816

BAYERISCHE AKADEMIE DER WISSENSCHAFTEN

Germany

EU Contribution

€ 347 160

FORSCHUNGSZENTRUM JULICH GMBH

Germany

EU Contribution

€ 369 238

UNIVERSIDAD DE CANTABRIA

Spain

EU Contribution

€ 287 200

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

France

EU Contribution

€ 642 518

INSTITUT NATIONAL DE RECHERCHE ENINFORMATIQUE ET AUTOMATIQUE

France

EU Contribution

€ 332 139

STMICROELECTRONICS GRENOBLE 2 SAS

France

BULL SAS

France

EU Contribution

€ 953 462

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS

France

EU Contribution

€ 462 836

CINECA CONSORZIO INTERUNIVERSITARIO

Italy

EU Contribution

€ 202 441

UNIVERSITY OF BRISTOL

United Kingdom

EU Contribution

€ 346 720

ALLINEA SOFTWARE LIMITED

United Kingdom

EU Contribution

€ 231 200

ARM LIMITED

United Kingdom

EU Contribution

€ 1 096 631

UNIVERSITE JOSEPH FOURIER GRENOBLE 1

France

EU Contribution

€ 219 972

UNIVERSITE MONTPELLIER 2 SCIENCES ET TECHNIQUES

France

EU Contribution

€ 228 790

INSTITUT POLYTECHNIQUE DE BORDEAUX

France

EU Contribution

€ 159 217

UNIVERSITE DE MONTPELLIER

France

Project information

Grant agreement ID: 610402

Status

Closed project

  • Start date

    1 October 2013

  • End date

    31 January 2017

Funded under:

FP7-ICT

  • Overall budget:

    € 11 480 272

  • EU contribution

    € 8 057 000

Coordinated by:

BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION

Spain