Periodic Reporting for period 2 - DOMINO (Design Oriented ModellINg for flexible electrOnics)
Reporting period: 2016-12-01 to 2018-11-30
The scientific, technical and industrial objectives of our project are to:
· Create generic open source compact models for OTFTs and AOS TFTs targeted at innovative printed and flexible electronics applications.
· Validate the models of OTFT and AOS TFT technologies (for device and circuit design level) developed by manufacturing partners.
· Integrate the model in commercial EDA (Electron Design Automation) tools and implement standardised parameter extraction standards.
· Demonstrate the model for the design of printed or flexible OTFT and AOS TFT circuits.
· Develop a prototype printed or flexible circuit for model validation.
· Disseminate the model for the European Thin, Organic and Large Area Electronics design community.
The main impact of our project is to bring a change of flexible electronics development paradigm, from a technology push to an application driven mode, by providing accurate compact OTFT and AOS TFT models to designers.
During the course of this project partners will undertake a number of fabrication, measurement and design iterations to address issues in the behaviour and modelling of organic and oxide semiconductor devices. These are aimed at improving the performance of these devices and circuits incorporating them.
Fundamental material dependent microscopic and transport models will be extended to physical macroscopic device level models, from which novel compact models will be developed and implemented for circuit design. The research carried out in this project will lead to the development of enhanced device level and circuit level models. This will result in accurate models that will be made accessible to the industry and future designers.
The main results obtained are:
1. Design-oriented compact model for OTFTs and AOS TFTs, experimentally validated
2. Improved OTFT and AOS TFT model parameter extraction procedures.
3. Charge-based models for OTFTs and AOS TFTs
4. Capacitance models for OTFTs and AOS TFTs taking into account frequency dispersion.
5. Identification and modeling of top overlap effects in ESL IGZO TFTs.
6. Identification and analytical model of 1/f noise mechanisms in OTFTs and ESL IGZO , validated experimentally.
9. Analytical modeling of injection contact effects in OTFTs.
10. Analysis and modelling of OTFTs and AOS TFTs I-V and C-V characteristics from 150 to 350 K.
13. Modeling of bias and illumination stress in IGZO TFTs.
14. OTFT and AOS TFT models written in Verilog-A codes and validated in circuit simulation.
15. Successful comparison between experimental and simulated circuit performances using Verilog-A model codes.
The main results, which are the final device models, will be exploited. The first version of the AOS TFT model developed by URV is already available in Silvaco EDA tools as MOTFT model. The improved model, resulting from the collaboration of URV and UCAM, will also be incorporated to SIlvaco EDA tools as an updated MOTFT model. URV will be in charge of the future improvement in the coming years for commercial EDA tools.
The OTFT model developed by THM and URV, with additional features made by XTEC, will also be incorporated to Silvaco EDA tools as an updated version of their existing UOTFT model. THM will be in charge of the future improvement in the coming years for commercial EDA tools.
A total of 27 papers related to DOMINO were published or accepted in international journals, including high impact ones. Besides, , the IEEE Journal of the Electron Devices Society (which is open-access) invited the DOMINO Coordinator to submit two review papers presenting the main results obtained by the DOMINO Consortium. On the other hand, a total of 52 talks were presented in international conferences, and six more papers about OTFT and AOS TFT compact model which have been submitted to international journals
Two training events and two workshops were carried out during the course of the project.
Concerning AOS TFTs, we developed the first compact model for the drain current and charges and capacitances considering all conduction mechanisms. For the first time, we identified and analyzed the effect of the top overlap in etch-stop layer (ESL) IGZO TFTs. We also identified and developed analytical models for the bias and illumination stress in AOS TFTs. We presented the first analysis of the temperature dependence of the conduction mechanisms,. A quasi-crystalline behavior (with carrier scattering leading to mobility degradation) was found for the first time in IGZO TFTs at temperatures higher than a certain threshold. Furthermore, for the first time we analyzed the mechanisms of 1/f noise in ESL IGZO TFTs and we concluded that i is mostly due to carrier number fluctuations. We also developed compact models for 1/f noise models in ESL IGZO TFTs, which exhibited good accuracy with the measurements at different temperatures.
The Compact Modeling Coalition is planning to open a call for proposals of a standard compact TFT (possible AOS TFT) model. If this happens, the DOMINO consortium will submit our model. If it wins the contest, it will become the main standard AOS TFT model used by foundries, design houses, and EDA vendors. But even if our model does not win the contest, very probably will still be considered one of the main AOS TFT models, and therefore exploited by companies.
The knowledge generated by the project will contribute to improve the research and innovation potential of the participating institutions, keeping them at the forefront of flexible electronics research, and therefore, will be instrumental to strengthen flexible electronics research and innovation within Europe, and also worldwide.