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Energy-efficient Heterogeneous COmputing at exaSCALE

Energy-efficient Heterogeneous COmputing at exaSCALE

Objective

In order to reach exascale performance current HPC servers need to be improved. Simple scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementation technology, what is needed is to refine the HPC application development as well as the architecture of the future HPC systems.

ECOSCALE tackles this challenge by proposing a scalable programming environment and hardware architecture tailored to the characteristics and trends of current and future HPC applications, reducing significantly the data traffic as well as the energy consumption and delays. We first propose a novel heterogeneous energy-efficient hierarchical architecture and a hybrid MPI+OpenCL programming environment and runtime system. The proposed architecture, programming model and runtime system follows a hierarchical approach where the system is partitioned into multiple autonomous Workers (i.e. compute nodes). Workers are interconnected in a tree-like structure in order to form larger Partitioned Global Address Space (PGAS) partitions, which are further hierarchically interconnected via an MPI protocol.

Secondly, to further increase the energy efficiency of the system as well as its resilience, the Workers will employ reconfigurable accelerators that can perform coherent memory accesses in the virtual address space utilizing an IOMMU. The ECOSCALE architecture will support shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, and, more importantly, automated hardware synthesis of these resources from an OpenCL-based programming model.

We follow a co-design approach that spans a scalable HPC hardware platform, a middleware layer, a programming and a runtime environment as well as a high-level design environment for mapping applications onto the system. A proof of concept prototype and a simulator will be built in order to run two real-world HPC applications and several benchmarks.
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Coordinator

TELECOMMUNICATION SYSTEMS INSTITUTE

Address

Technical University Of Crete Campus - Kounoupidiana
73100 Chania

Greece

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 688 625,01

Participants (8)

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THE QUEEN'S UNIVERSITY OF BELFAST

United Kingdom

EU Contribution

€ 710 000

STMICROELECTRONICS GRENOBLE 2 SAS

France

EU Contribution

€ 139 307,78

ACCIONA CONSTRUCCION SA

Spain

EU Contribution

€ 380 000

THE UNIVERSITY OF MANCHESTER

United Kingdom

EU Contribution

€ 507 865

POLITECNICO DI TORINO

Italy

EU Contribution

€ 517 500

CHALMERS TEKNISKA HOEGSKOLA AB

Sweden

EU Contribution

€ 570 632,50

SYNELIXIS LYSEIS PLIROFORIKIS AUTOMATISMOU & TILEPIKOINONION ANONIMI ETAIRIA

Greece

EU Contribution

€ 460 750

FOUNDATION FOR RESEARCH AND TECHNOLOGY HELLAS

Greece

EU Contribution

€ 262 717,21

Project information

Grant agreement ID: 671632

Status

Ongoing project

  • Start date

    1 October 2015

  • End date

    31 July 2019

Funded under:

H2020-EU.1.2.2.

  • Overall budget:

    € 4 237 397,50

  • EU contribution

    € 4 237 397,50

Coordinated by:

TELECOMMUNICATION SYSTEMS INSTITUTE

Greece