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Exploiting eXascale Technology with Reconfigurable Architectures

Exploiting eXascale Technology with Reconfigurable Architectures

Objective

To handle the stringent performance requirements of future exascale High Performance Computing (HPC) applications, HPC systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require reconfiguration as an intrinsic feature, so that specific HPC application features can be optimally accelerated at all times, even if they regularly change over time.
In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in from the start. The idea is to enable the efficient co-design and joint optimization of architecture, tools, applications, and reconfiguration technology in order to prepare for the necessary HPC hardware nodes of the future.
The project EXTRA covers the complete chain from architecture up to the application:
• More coarse-grain reconfigurable architectures that allow reconfiguration on higher functionality levels and therefore provide much faster reconfiguration than at the bit level.
• The development of just-in time synthesis tools that are optimized for fast (but still efficient) re-synthesis of application phases to new, specialized implementations through reconfiguration.
• The optimization of applications that maximally exploit reconfiguration.
• Suggestions for improvements to reconfigurable technologies to enable the proposed reconfiguration of the architectures.
In conclusion, EXTRA focuses on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new reconfigurable architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a design concept, and applications that are tuned to maximally exploit run-time reconfiguration techniques.
Our goal is to provide the European platform for run-time reconfiguration to maintain Europe’s competitive edge and leadership in run-time reconfigurable computing.
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Coordinator

UNIVERSITEIT GENT

Address

Sint Pietersnieuwstraat 25
9000 Gent

Belgium

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 530 296

Participants (8)

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TELECOMMUNICATION SYSTEMS INSTITUTE

Greece

EU Contribution

€ 420 000

IMPERIAL COLLEGE OF SCIENCE TECHNOLOGY AND MEDICINE

United Kingdom

EU Contribution

€ 559 080

POLITECNICO DI MILANO

Italy

EU Contribution

€ 451 250

UNIVERSITEIT VAN AMSTERDAM

Netherlands

EU Contribution

€ 533 836

RUHR-UNIVERSITAET BOCHUM

Germany

EU Contribution

€ 476 250

MAXELER TECHNOLOGIES LIMITED

United Kingdom

EU Contribution

€ 415 000

SYNELIXIS LYSEIS PLIROFORIKIS AUTOMATISMOU & TILEPIKOINONION ANONIMI ETAIRIA

Greece

EU Contribution

€ 305 812,50

THE CHANCELLOR MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE

United Kingdom

EU Contribution

€ 298 406

Project information

Grant agreement ID: 671653

Status

Closed project

  • Start date

    1 September 2015

  • End date

    31 August 2018

Funded under:

H2020-EU.1.2.2.

  • Overall budget:

    € 3 989 931,25

  • EU contribution

    € 3 989 930,50

Coordinated by:

UNIVERSITEIT GENT

Belgium