Periodic Reporting for period 2 - L3MATRIX (Large Scale Silicon Photonics Matrix for Low Power and Low Cost Data Centers)
Reporting period: 2017-06-01 to 2019-05-31
The L3MATRIX project provided novel technological innovations in the fields of silicon photonics (SiP) and 3D device integration. The project will develop a novel SiP matrix with a scale larger than any similar device with more than 100 modulators on a single chip and will integrate embedded laser sources with a logic chip thus breaking the limitations on the bandwidth-distance product.
A novel approach has been used with embedded III-V sources on the SOI substrate which will eliminate the need to use an external light source for the modulators. L3MATRIX provided a new method of building switching elements that are both high radix and have an extended bandwidth of 25 Gb/s in single mode fibres and waveguides with low latency. The power consumption of DC networks built with these devices is 10-fold lower compared to the conventional technology. The outcome of this approach is that large networks, in the Pb/s scale can be built as a single stage, non-blocking network.
• To fabricate a large scale, two-dimensional Silicon Photonics chip with 128 lanes on 100mm2 requiring a density of ~0.8mm2 per channel
• Integrate 128 hybrid silicon III-V laser sources in a 100mm2
• Vertical (3D) chip package for integration of the Silicon Photonic chip on a digital CMOS chip using enabling a total bandwidth of 3.2Tb/s in an area of 100mm2 or less.
• Vertical fibre coupling of fibre arrays with 128fibres with loss less than 3dB per fibre.
• Improvement of the power efficiency to the 3pJ/bit range
• Reduce the port-to-port latency to less than 20ns
• Scalable data centre architecture into the Pb/s scale
• Data centre usage scenario that allows direct fibre-to-ASIC termination of commercial single mode transceivers reducing the cost for DEC equipment with more than 40%
L3MATRIX addressed the research and innovation actions of the H2020 call ICT-27-2015 with the topics “Optical communication for data centres” and “PIC technology”. In the following paragraphs, we indicate which of the specific challenges have been addressed.
1. On-chip Parallel Optical Interconnects
• Any logic functionality may be designed into the mixed signal ASIC
• Low power SerDes arrays (no need to drive lossy PCB traces)
• Overcomes the chip radix limit. Highest possible density per mm2
• Maximizes the bandwidth x distance product; enables both small (4 lanes) and very large (~500 lanes) devices with BW in the 20Tbps range per ASIC!
• Two-dimensional Silicon Photonics matrix is assembled directly on top of an ASIC
• ASIC has all of the required analog functionality + any logic block (e.g. FEC, MAC)
• The SiP matrix is scalable, support for 256 lanes is possible
• 2D fiber arrays are assembled above the optical matrices
• The package supports both the ASIC and optical coupling to the fiber array
• The solution supports CWDM4 and PSM4
2. Co-package of photonics with digital CMOS
• The switch ASIC and 2-4 ‘optical I/O ASICs’ are co-packaged on a single MCM/interposer
• Fiber bundles connect the module and the front panel passive fiber connectors
The L3MATRIX vision is implemented with the following approach:
• 2D SiP matrix (4×16) cells. Each cell is optically and electrically isolated from its neighbours
• The unit cell is a full SiP transmitter or receiver with embedded DFB laser
• The lasers in each row have a CWDM wavelength. The output of each column is multiplexed and fiber coupled
• The 2D SiP is back illuminating with a Silicon microlens assembled on the back surface to assist in fiber coupling
• The analog chip drives the MZI modulator and supplies DC bias to the DFB lasers
Within the 42 Months, L3MATRIX managed to reinforce its dissemination tools by updating its website and social media accounts, release several newsletters and present a large number of publications to journals and invited talks to prestigious conferences in optical technologies.
Concerning the dissemination of L3MATRIX foreground knowledge to the scientific community, the consortium managed to present 45 publications to peer-reviewed journals and over 50 “other dissemination actions” that include invited talks to prestigious conferences in optical technologies, workshop presentations, webinars and others. The consortium filed 6 patents during the project lifetime.
The outcome of the L3MATRIX project was to demonstrate the basic building blocks of a co-packaged optical system. Two dimensional silicon photonics arrays with 64 modulators were fabricated in the fab. Novel modulation schemes based on slow light modulation have been developed to assist in achieving efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Packaging of these 2D photonic arrays in a chiplet configuration has been demonstrated using a vertical integration approach in which the optical interconnect matrix was flipchip assembled on top of CMOS mimic chip with 2D vertical fiber coupling. The optical chiplet was further assembled on a substrate to facilitate integration with the multi-chip module of the co-packaged system with a switch surround by several such optical chiplets
A proactive Intellectual Property Rights management strategy was successfully deployed resulting in L3MATRIX foreground innovations being captured in 6 patents.
Regarding the dissemination of L3MATRIX foreground knowledge to the scientific community, during the lifetime of the project, more than 45 publications in journals were generated and more than 50 “other dissemination actions” that included invited talks to prestigious conferences in photonics, workshop presentations etc. Moreover, L3MATRIX organized 3 successful Symposia on Optical Interconnects with more than 150 attendees at each event.
The main project results and technologies are now available to small and medium-sized enterprises for further development, for deep characterization of system embedded photonic interconnect and for validation in data centre environments within ‘PhoxLab - European Photonics Innovation Hub for Optical Interconnects’ at the Fraunhofer IZM in Berlin.