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Revolutionary embedded memory for internet of things devices and energy reduction

Periodic Reporting for period 1 - REMINDER (Revolutionary embedded memory for internet of things devices and energy reduction)

Reporting period: 2016-01-01 to 2017-06-30

To achieve the objectives of REMINDER, the project structure is founded on three main
pillars:
1. Investigation (concept, design, characterization, simulation, modelling), selection and
optimization of a Floating-Body memory bit cell in terms of low power and low voltage, high
reliability, robustness (variability), speed, reduced footprint and cost. Fabrication of selected
bit cells with FDSOI and III-V technologies.
2. Design and fabrication in FD28 and FD14 technology nodes of a memory matrix based on
the optimized bitcells developed in the first pillar. Matrix memory subcircuits, blocks and
architectures will be carefully analysed from the power-consumption point of view. In
addition, variability tolerant design techniques underpinned by variability analysis and
statistical simulation technology will be considered.
3. Demonstration of a system on chip (SoC) application using the developed memory
solution and benchmarking with alternative embedded memory blocks.

Technical objectives
• Tech 1: Investigation, selection and optimization of a memory bit cell in terms of low
power and low voltage, high reliability, robustness (variability), speed, reduced
footprint and cost based on Floating-Body SOI concept.
• Tech 2: Design and fabrication in FD28 and FD14 technology nodes of a memory
matrix based on the optimized bit-cells.
• Tech 3: Demonstration of the developed memory solution and benchmarking with
alternative embedded memory blocks.
Scientific Objectives
• Sci 1: Electrical characterization: from ultimate CMOS to Beyond Si CMOS.
• Sci 2: Advanced numerical simulation: Top-down hierarchical simulation
• Sci 3: Variability and reliability issues of advanced nanodevices
• Sci 4: Development of ultra-low power memory solutions
Strategic Objectives
• Stra 1: Reinforce the European manufacturing position by gaining leadership
through the demonstration of ultra-low-power IP blocks for IoT edge devices,
wearables and health systems using FDSOI technologies developed by
STMicroelectronics.
• Stra 2: Demonstrate the suitability of emerging III-V MOSFETs, nanowire FETs and
3D circuits for ultralow-power applications, extending the FDSOI technology.
• Stra 3: This project will deliver significant strategic benefit to the partners and the EU
through the research and delivery of a new memory solution which will offer
competitive advantage to EU companies by a) improved performance, specifically
lower power; b) lower cost, specifically through a simpler process and smaller area.
According to the Workplan, the main objectives for the first reporting period (M1-M18) of REMINDER project were:

1. Kick-off of the project.
2. Selection of the memory cell among the three candidates to build an embedded memory matrix, and later, the committed demonstrator.
3. Extensive electrical characterization of selected devices and calibration of TCAD tools.
4. Extensive TCAD simulation of selected devices (Z2FET).
5. Design and fabrication of REMINDER-dedicated devices.
6. Compact modelling activities for the selected cell.
7. Starting the design of a prototype of an embedded DRAM memory matrix using Z2FET as building block.
8. Simulation and characterization of 3D NWs and III-V semiconductors memory cells.
9. Dissemination and Exploitation activities (publications and first industrial workshop organization).
10. Continuous reporting to the EU.
The semiconductor industry needs, more than ever, new memory paradigms to tackle with
the storage, processing, energy consumption and cost demands of the integrated circuits
oriented to the Internet of Things (IoT). The REMINDER project is ultimately focused to
develop an embedded Floating Body DRAM solution for IoT cut-edge devices, i.e. the
pursued memory block will be optimized for ultra-low-power consumption, variability
immunity, and low cost, in addition to the footprint miniaturization. The pragmatic approach
for quick lab-to-market demonstration is to use the established FDSOI technology, without
introducing alternative materials or new steps in the fabrication process (different from the
ones already necessary to fabricate the rest of blocks in the system). In parallel, we will also
define longer-term FB-DRAM solutions using emerging technologies that are not yet
established (III-V, NWs, and SiGe).
Picture of the silicon wafer with Z2FET devices and memory matrix
Schematic of a Z2FET device