Periodic Reporting for period 2 - WIPE (Wafer scale Integration of Photonics and Electronics)
Reporting period: 2017-07-01 to 2019-06-30
The WIPE project aims at developing a technology by which electronic chips (ICs) and photonic chips (PICs) are very intimately placed on top of each other. The ICs contain the driver, receiver and control electronics for the PIC. The PIC generates the photonic signals and can be directly connected to optical fibres. It is the aim to interconnect ICs and PICs when they are still embedded in the production 'wafer' of semiconductive material. This technology of ‘wafer scale heterogeneous integration’ enables the creation of high-performance and high-density photonic-electronic (photronic) modules having a lower energy consumption, lower complexity and lower cost compared to modules using more traditional interconnection techniques of the separate chips, like wire bonding and laser welding of fibre connections.
Next to the new bonding technology of ICs and PICs, an integrated module design technology is developed for efficient co-design of ICs and PICs so that they exactly fit onto each other. A library consisting of photonic/electronic standard modules, is created leveraging the process design kits (PDKs) of the most important European manufacturers of photonic chips in combination with a powerful BiCMOS IC-manufaction technology. These tools are of significant importance to industry, since they offer photronic module designers a standardised approach that highly facilitates the module design for SMEs and affordable manufacturing by the photonic and electronic foundries. The PDK is demonstrated by the prototyping of a 400Gb/s transceiver for data center applications as mentioned.
In doing so, the WIPE project aims at bringing photonics to a new level by developing a concept that can be well industrialised. This sustains EU leadership in photonics.
1. the experimentation phase of interconnecting the ICs and PICs ('sticking' them onto each other) with great accuracy. In this phase the interconnection process is studied and optimized, while the joint properties of the connected chips (esp. the properties of the electronic interconnects and the connection of the PIC to the fibre) are studied and characterized.
2. the development of a one channel (25 Gbit/s) working device. Both the IC and PIC need to be co-designed for a proper functioning when interconnected. Electronical, optical and thermal properties of the chips need to be considered carefully in view of the very different properties when mounted on top of each other. Additonal process development is conducted.
3. the demonstration of an eight channel device (400 Gbit/s) delivering the final proof of the pudding of the technology.
Currently at the half time of the project, process research of phase 1 is still in progress. In the meantime, IC and PIC design for the stage 2 prototype is nearly completed. The technology development of the wafer scale integration is somewhat delayed due to several technical challenges which needs to be solved before the actual bonding process can be applied and evaluated.
The technology as developed within the WIPE-project however can be wider applied than just datacom applications. In every device where PICs and ICs must be combined, the WIPE solution is an option to create more compact, better performing and cheaper solutions.
Many parties can benefit from the WIPE-technology. It opens the market for new devices which could not be obtained because traditional technologies are too lumpy, too expensive or too energy consuming. The technology will also provide an impulse to the European photonic integration industry; Europe has been active in this field for many years and is running several years ahead of competitors. However, the lack of an adequate integration technology of ICs and PICs has been a draw back. The partners cooperating in WIPE hope that this technology will boost industry and academia to expand their commercial and research activities in integrated photonics.