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Ion-irradiation-induced Si Nanodot Self-Assembly for Hybrid SET-CMOS Technology

Periodic Reporting for period 2 - IONS4SET (Ion-irradiation-induced Si Nanodot Self-Assembly for Hybrid SET-CMOS Technology)

Reporting period: 2017-08-01 to 2019-01-31

Billions of tiny computers (www.gartner.com) that can sense and communicate from anywhere are coming online, creating the “Internet of Things” (IoT). Despite their continu¬ously extended functionalities, low-power consumption of these devices is required to enable sufficiently long operation lifetime. In combination with the development of high-capacity batteries, the reduction of the specific power consumption of main computer components is a key challenge. To tackle this aim, the project IONS4SET is related to reduce the power con¬sumption of circuits enabling processor and switching functionalities for advanced compu¬tation and communication devices.
It is well-known that Single Electron Transistors (SET) delivers an approach for extremely low energy dissipation devices. The overall objective of the IONS4SET project is to demonstrate the manufacturability of Si quantum dot based SETs in a CMOS-compatible technology. The SET will work at room temperature (RT) and the combination with common field effect transistors (FET) will allow the communication to external devices.
The RT operation of the SET requires Si nanodots of < 3 nm size to enable quantum confinement and Coulomb blockade. A bottom-up self-assembly process will be developed and used in IONS4SET which provides (i) the controlled self-assembly of single small Si nanodots and, (ii) the self-alignment of the Si dot with respect to the source and drain and tunneling distances of < 2 nm. The reliable fabrication process of single Si quantum dots is based on ion irradiation through a Si/SiO2 (6 nm) /Si layer stack and subsequent thermal treatment to activate the self-assembling. The formation of single Si dots requires a confinement of the ion beam mixed volume within the oxide which is ensured by the use of Si/SiOx/Si nanopillars of < 15 nm diameter.

The SET to be fabricated within IONS4SET exhibits a gate-all-around (GAA) vertical nanowire structure where the nanopillars together with the embedded Si quantum dots are the key elements (see Figure, left). Finally, a hybrid SET/FET demonstrator will be fabricated. The FET integration is realized with a less-risk approach to enable the full functionality of the device (see Figure, right) and to allow an assessment of the predicted low-energy dissipation of the approach considered in IONS4SET.
The overall work can be sub-divided into three project stages: I. Realization of a single Si nanodot (ND) in a stacked Si/SiO2/Si nanopillar (NP), II. Processing and characterization of gate-all-around nanopillar SETs with Si NDs, III. Fabrication and characterization of a hybrid SET/FET demonstrator. All WPs contributed to the project progress which is confirmed by the successful realization of Milestones 1, 2 and 3. In the following an overview about the work and achieved progress is given:

1. Self-assembly of single Si NDs in SiO2 films based on ion beam mixing at interfaces
Initially, it was experimentally confirmed that – as predicted by simulations – a Si nanocluster band in SiO2 appears after ion irradiation and subsequent annealing of a Si/SiO2/Si stack if the sandwiched SiO2 film is sufficiently thin (5 – 7 nm). Subsequent investigations were directed at the shrinkage of the nanocluster band towards single Si NDs. The main approach is the confinement of the mixed volume by using Si/SiO2/Si NPs. This has been experimentally validated by local irradiation using FIB equipment. As NPs with a diameter below 30 nm were available, broad beam Si implantation and subsequent rapid thermal annealing have been applied for Si ND formation which was proven by energy-filtered TEM. The realization of tunnel distances between the Si ND and the drain and source regions are of most relevance for the functionality of the SET. The experimental optimization of parameters like oxide thickness, nanodot size, mixing conditions or thermal budget, has been guided by extensive computer simulations of ion beam mixing, phase separation and ND formation. Suitable parameters have been found to enable the reliable formation of Si quantum dots in a thin SiO2 film.

2. Process development for sub-30 nm NPs from stacked Si/SiO2/Si by electron beam lithography (EBL) and/or directed self-assembly technology (DSA)
Two approaches were intended in the DoA: (i) electron Beam Lithography (EBL) and Reactive Ion Etching (RIE) and, (ii) Directed Self-Assembly Technology (DSA). Within the reporting period the pillar fabrication was focused to the EBL/RIE approach. The target was to realize a nanopillar of sub-30 nm diameter stacked of 25 nm poly-Si / 6 nm SiO2 / 25 nm crystalline Si. EBL using a hard mask approach has been found to provide NPs down to a CD of 20 nm. Further shrinking of nanopillars diamater to a targeted size of about 120 nm is possible by using the sacrificial oxidation technique based on low-temperature plasma oxidation technique. Stand-alone Si/SiO2/Si pillars of 10 nm diameter and 70 nm height with Si NDs in the oxide have been successfully prepared on wafer level. These pillars are ready to be integrated in the SET process flow.

3. Technology development for a gate-all-around SET
Parallel to ND/NP fabrication, WP6 has performed work aimed to develop processes and methods for the integration of SET devices into CMOS circuits that can later be transferred to an industrial foundry. A suitable CMOS compatible process flow to fabricate a stand-alone SETs and an integrated SET/FET circuit were developed. During the first review meeting in Brussels in October 2016, the external experts recommended to focus the activities within next months to the process development for a fully contacted SET. As a consequence, key geometrical and structural parameters as well as preliminary device properties have been defined and single process step development has been performed. The use of hydrogen-silsesquioxane (HSQ) for the intermediate insulating layers and titanium nitride (TiN) as gate electrode are key technological steps. Certain critical risks have been successfully mitigated, but this additional work leads to a time delay delay of about 6 months for SET fabrication.

4. Management and dissemination activities
The project requires a close interaction of predictive simulation work, process development, preparation of test and device compon
All expected impact factors, as pointed out in section 2.1 of the DoA are still valid. Presently there is no need for an update.
Si/SiO2/Si nanopillar with an single Si nanodot in the oxide
Sketch of the gate-all-around SET (left) and the hybrid SET/FET (right).