Skip to main content

3C-SiC Hetero-epitaxiALLy grown on silicon compliancE substrates and 3C-SiC substrates for sustaiNable wide-band-Gap powEr devices

Periodic Reporting for period 2 - CHALLENGE (3C-SiC Hetero-epitaxiALLy grown on silicon compliancE substrates and 3C-SiC substrates for sustaiNable wide-band-Gap powEr devices)

Reporting period: 2018-07-01 to 2019-12-31

We propose a new approach to improve the quality and to reduce stress: it is necessary to modify the structure of the substrate (compliance substrate) in order to force the system to reduce the defects while increasing the thickness of the layer.

Furthermore, by using the typical bulk growth techniques used for 4H-SiC it is possible to grow bulk 3C-SiC wafers, improving considerably the quality of the material.

Currently silicon is the material of choice for power electronic applications where the inevitable power dissipation requires the use of very heavy and expensive heat sinks. The purpose of these undesirable heat sinks is to manage the device junction temperature, allowing operation in the range where Si devices are able to function. The reason is simple - the low Si band-gap.

The best alternative for these applications is 3C-SiC.
In this first eighteen months of the project the activity has been concentrated essentially on the development of the compliance substrates, on the hetero-epitaxial and bulk growth. Several defects (voids, protrusions, stacking faults, …) have been studied in detail by different experimental techniques, to try to improve the quality of the material. Some effort has been used to try to understand and reduce the stress in the grown layer and the final bow. The effect of different compliance substrates on the substrate bow has been also analysed in detail with the comparison between experimental and simulation results. Also the development of the processing (metallization, gate oxidation, ion implantation, …) necessary for the realization of the devices has started in the last part of the first year.
Some interesting results have been obtained in the reduction of voids at the 3C-SiC/Si interface, the reduction of protrusions both in hetero-epitaxial growth and in bulk growth, in the understanding of SFs behaviour and in the reduction of this kind of defects in bulk growth. Also the modelling of stress in compliance substrates has given new understanding on the growth process.
The samples for evaluation have been fabricated. Then, defect density, internal stress, and configuration of structural defect will be revealed till end of October. The fine-tuning of 3C-SiC growth condition will be carried out referring the evaluation results. Finally, the defect density will be reduced below 100/cm keeping the internal stress lower than 200MPa.
CHALLENGE logo