Objective Conventional analog Phase-Locked Loop (PLL) occupies large area and is difficult to be reconfigured due to a bulky loop filter. In 2005, phase-domain all-digital phase-locked-loop (ADPLL) was proposed. It measured output phase of digitally controlled oscillator (DCO) using a time-to-digital converter (TDC). Unfortunately, designing fine-resolution TDC and wide dynamic range is power-consuming. In this project, instead of utilizing single sampling point per reference clock, we propose to oversample and digitize oscillator oscillator waveform which will produce enough digital samples to reconstruct, now in digital domain, the waveform and compare against a model waveform which will give precise frequency/phase and amplitude information. Thus, it is called, wave-locked loop (WLL) that will result in low-in-band phase noise, fast lock time, and wide-loop bandwidth that is no longer limited by reference clock. Preliminary data shows finer than 1-degree phase resolution even with 10% delay error in sampling clocks, and distortion from input waveform. This shows possibility to break the tradeoff in traditional TDC and improve robustness over PVT variations. Moreover, the design of building blocks which includes low-flicker-noise mm-wave LC Digitally-Controlled Oscillator (DCO) and small-sized ring oscillator with phase noise filtering will be investigated. Thus, this fellowship program studies an innovative frequency synthesizer and clock generation systems using wave-locked loop, which includes the study of oversampling of oscillator waveform for fine phase detection, the study of phase-noise reduction in ring oscillator using discrete-time filtering, the study of mm-wave oscillator with flicker noise corner reduction, and system integration for wave-locked loop system. The proposed synthesizer will be tapeout using advanced CMOS technology and will be measured to verify their performance. Fields of science engineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationstelecommunications networksmobile network5Gengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technologybluetoothengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationstelecommunications networksmobile network4Gengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technologyradarengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsmobile phones Keywords CMOS Integrated Circuit Radio Frequency RFIC Frequency synthesizer Phase-locked loop (PLL) All-digital phase-locked loop (ADPLL) Digitally-Controlled Oscillator (DCO) Phase Noise Jitter Programme(s) H2020-EU.1.3. - EXCELLENT SCIENCE - Marie Skłodowska-Curie Actions Main Programme H2020-EU.1.3.2. - Nurturing excellence by means of cross-border and cross-sector mobility Topic(s) MSCA-IF-2016 - Individual Fellowships Call for proposal H2020-MSCA-IF-2016 See other projects for this call Funding Scheme MSCA-IF - Marie Skłodowska-Curie Individual Fellowships (IF) Coordinator UNIVERSITY COLLEGE DUBLIN, NATIONAL UNIVERSITY OF IRELAND, DUBLIN Net EU contribution € 175 866,00 Address BELFIELD 4 Dublin Ireland See on map Region Ireland Eastern and Midland Dublin Activity type Higher or Secondary Education Establishments Links Contact the organisation Opens in new window Website Opens in new window Participation in EU R&I programmes Opens in new window HORIZON collaboration network Opens in new window Total cost € 175 866,00