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Modeling critical reliability issues in VLSI technologies beyond 2020

Modeling critical reliability issues in VLSI technologies beyond 2020

Objective

This proposal presents an interdisciplinary, forward looking, training-by-research plan in the field of physical reliability modeling of emerging transistors and materials beyond 2020. Its main goal is development and validation of a simulation framework which self-consistently considers the main reliability phenomena including bias temperature instability, hot-carrier degradation, and self-heating. These effects were suggested to be the response of interface and oxide defects/precursors which can be activated by different driving forces determined by device operating conditions and specifics of the device topology. Thus, the core of this project will be put on a detailed microscopic description of the properties of defects/precursors, which will be studied experimentally and theoretically.
Within this defect-centric paradigm we will address reliability issues in devices with emerging architectures, i.e. fin and nanowire transistors, high-k gate dielectrics, and high mobility channel materials such as SiGe, Ge, and III-V alloys. The unifying model building on the microscopic defect properties will be validated over a wide range of device bias conditions. We will capture the parasitic effect of self-heating which has a strong impact on the energetic distribution of hot carriers and hence on hot-carrier degradation. Special attention will be paid to time-dependent variability of device characteristics which is a response of nanoscale devices on activation/deactivation of individual defects.
Knowledge acquired within this project will be valuable for applied and fundamental physics, material science, computational chemistry, electrical engineering, VLSI technology, and circuit design. The research and training activities will enhance applicant’s future career by broadening his professional skills and expertise, expose him to industrial requirements, and open new perspectives for future collaboration with industry.
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Coordinator

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

Address

Kapeldreef 75
3001 Leuven

Belgium

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 172 800

Project information

Grant agreement ID: 794950

Status

Ongoing project

  • Start date

    22 August 2018

  • End date

    21 August 2020

Funded under:

H2020-EU.1.3.2.

  • Overall budget:

    € 172 800

  • EU contribution

    € 172 800

Coordinated by:

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

Belgium