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Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics

Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics

Objective

The future miniaturisation of electronic circuits following Moore’s law will require the introduction of increasingly disruptive
technologies to limit power consumption and optimise performance per circuit area. CHIRON envisions spin wave computing
to complement and eventually replace CMOS in future microelectronics. Spin wave computing is a paradigm-shifting
technology that uses the interference of spin waves for computation. Spin wave computing has the potential for significant
power and area reduction per computing throughput while reducing cost by alleviating lithography requirements. As a first
step towards the vision of a full spin wave computer, CHIRON envisions hybrid spin wave–CMOS circuits that can be readily
integrated alongside CMOS.
CHIRON targets a proof of principle of the essential elements for spin wave computing by an interdisciplinary approach
joining partners with expertise in material science, physics, nano-manufacturing, electrical engineering, device simulation,
and circuit design. CHIRON will fabricate basic logic gates, such as inverters and majority gates, demonstrate their
operation, and assess their performance. As transducers between the CMOS and spin wave domains in hybrid circuits,
CHIRON will develop magnetoelectric and multiferroic nanoresonators, based on nanoscale bulk acoustic resonators, which
bear promise for high energy efficiency and large output signal. The targeted lateral scale (100 nm) and resonance
frequency (>10 GHz) bring such resonators to the frontier of nano-electromechanical systems (NEMS).
This technological proof of principle is complemented by the design of digital hybrid spin wave–CMOS circuits that show the
advantages of spin wave computing and can be integrated into a CMOS environment. Based on calibrated compact device
models, the performance of these circuits in terms of power, area, and throughput will be benchmarked against CMOS to
demonstrate their viability.

Coordinator

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

Address

Kapeldreef 75
3001 Leuven

Belgium

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 675 726,25

Participants (8)

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UNIVERSITE PARIS-SUD

France

EU Contribution

€ 441 025

TECHNISCHE UNIVERSITAET KAISERSLAUTERN

Germany

EU Contribution

€ 389 825

SOLMATES BV

Netherlands

EU Contribution

€ 512 875

INSTITUTUL NATIONAL DE CERCETAREDEZVOLTARE PENTRU MICROTEHNOLOGIE

Romania

EU Contribution

€ 220 437,50

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS

France

EU Contribution

€ 554 315

FOUNDATION FOR RESEARCH AND TECHNOLOGY HELLAS

Greece

EU Contribution

€ 283 750

THALES SA

France

EU Contribution

€ 254 330

TECHNISCHE UNIVERSITEIT DELFT

Netherlands

EU Contribution

€ 413 323,75

Project information

Grant agreement ID: 801055

Status

Ongoing project

  • Start date

    1 May 2018

  • End date

    30 April 2021

Funded under:

H2020-EU.1.2.1.

  • Overall budget:

    € 3 745 607,50

  • EU contribution

    € 3 745 607,50

Coordinated by:

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

Belgium