Open-source multicore processor for safety-critical applications receives commercial boost
RISC-V is a free and open-source hardware instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. The EU-funded De-RISC project aims to commercialise a multicore RISC-V system-on-a-chip design already developed by one project partner. The hardware development will be enhanced by enabling a safety-critical hypervisor (system software that guarantees non-interference between critical applications running over the same platform) to run in the project platform. The platform design takes into account multicore interference mitigation issues which are imperative for safety- and security-critical systems. It also has the potential to be implemented in field-programmable gate arrays and application-specific standard products. Importantly, there will be no imposed US export controls over the processor or the software. The project targets the use of the multicore RISC-V system-on-a-chip in safety-critical computers used in the space and the aviation fields.
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Funding SchemeIA - Innovation action