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Network Solution for Exascale Architectures

Project description

DEENESFRITPL

Paving the way to the new-generation European Interconnect for future Exascale systems

In future Exascale supercomputers, the interconnection network, which is already a critical component in HPC systems, might become the next big bottleneck. At the Exascale, the network should support massively parallel processing systems (hundreds of thousands of nodes), provide features allowing applications to scale efficiently at Exascale level and beyond, be prepared for new heterogeneous accelerators and compute units, and support datacentric and AI-related applications. The EU-funded RED-SEA project brings together the top European academic centres and the main European industrial forces in the domain of interconnection networks to tackle the interconnection bottleneck at Exascale. The RED-SEA consortium leverages key European technology, including BXI, the key production-proven European interconnection network, and works hand in hand with many related EU-funded projects.

Objective

In order to enable Exascale computing, next generation interconnection networks must scale to hundreds of thousands of nodes, and must provide features to also allow the HPC, HPDA, and AI applications to reach Exascale, while benefiting from new hardware and software trends.
To achieve this goal, the RED-SEA proposal gathers the key European R&D competences, by bringing together the top academic centres with the key European industrial forces in this domain. The project will leverage BXI, the key European Interconnect, which is in production and featured in Top 500 systems, with the aim to adapt it to the challenges of coming years.
RED-SEA will pave the way to the next generation of European Exascale interconnects, including the next generation of BXI, as follows:
i. specify the new architecture using hardware-software co-design and a set of applications representative of the new terrain of converging HPC, HPDA, and AI;
ii. test, evaluate, and/or implement the new architectural features at multiple levels, according to the nature of each of them, ranging from mathematical analysis and modelling, to simulation, or to emulation or implementation on FPGA testbeds;
iii. enable seamless communication within and between resource clusters, and therefore development of a high-performance low latency gateway, bridging seamlessly with Ethernet;
iv. add efficient network resource management, thus improving congestion resiliency, virtualization, adaptive routing, collective operations;
v. open the interconnect to new kinds of applications and hardware, with enhancements for end-to-end network services – from programming models to reliability, security, low-latency, and new processors;
vi. leverage open standards and compatible APIs to develop innovative reusable libraries and Fabrics management solutions.

We will work together with the other projects resulting from the EuroHPC-01-2019 call, especially with IO-SEA (topic b) and DEEP-SEA (topic d) if they get approved.

Fields of science

Keywords

Programme(s)

Topic(s)

Call for proposal

H2020-JTI-EuroHPC-2019-1

See other projects for this call

Funding Scheme

RIA - Research and Innovation action

Coordinator

BULL SAS
Net EU contribution
€ 1 948 150,00
Address
Rue jean jaures 68
78340 Les clayes sous bois
France

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Region
Ile-de-France Ile-de-France Yvelines
Activity type
Private for-profit entities (excluding Higher or Secondary Education Establishments)
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Other funding
€ 1 948 150,00

Participants (11)

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Last update: 3 March 2023
Record number: 232454

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European Union, 2023