Objetivo The projection system market is rapidly growing forced by two demands. First lower size and weight as well as the cost and second to integrate access to new multimedia interfaces like USB, TMDS, DVI, IEEE 1394 and to implement new advanced image processing features like a video text browser, displaying TV internet pages, non linear keystone correction and picture in picture. To get a share of the electronic projection system market as well as of the also enlarging market of high integrated multimedia projection IC's we decided to integrate our digital image processing device and the external CPU control into a system on chip solution (SOC). This enables us to reduce the cost, to customise the internal embedded CPU structure and at last to implement the new features described above. The new SOC will enable us to stay competitive on the projection systems market and will open the new market of projection IC's. This will also reduce the technical dependency from dominating Fare East and North American suppliers.Objectives:There are strong economical and technical objectives that forces us to this project. With the SOC we will stay competitive on the fast growing projection system market. This goal will be reached by reducing the number of board components as well as the board production costs. Another imported aspect is to get a share of the projection IC market. The integration of the CPU core enables us to combine our powerful hardware and software and to distribute both. This will enable us to create custom specific designs -based on software modifications- and to realise short time to market cycles. For technical side it enables us to customise the internal CPU environment, to optimise the CPU access to the other integrated modules and at last to implement new features. The knowledge we get from this project will give us a lasting improvement of our technical know-how. It will enable us to stay competitive economical as well as technical against Fare East and North American companies.Work description:Liesegang electronics (LE) acts as the project co-ordinator. The design specification and implementation of the SOC device will also be done by LE. The related staff to the project will be 1 project co-ordinator (related to the European Commission), 3 hardware and 2 software designers for the design and programming of the SOC device. The prototype board design will be done by a LE PCB design engineer with production and assembly outside. The Part of the subcontractor is to deliver the CPU core, to train the design engineers of LE in order to implement the core and to set it into operation and to generate the layout and production test data from gate level net list and test pattern as well as to deliver samples and volume production. The subcontractor will be selected after the evaluation phase and the specification of the IC design. The project will take about 17 month and is divided into 5 workpackages. The state of work will be reported every 6 months with a first review after 6 month and a final review at the end of project.Workpackage 1: This package includes all parts of monitoring to the European Commission and the later dissemination of the project results. In order to commercialise the later SOC device we plan to publish the design on SID and EURODISPLAY conferences.Workpackage 2: Time: 2 months- evaluation of the CPU core market- general hard and software specification- selection of hard and software tools demand by the projectWorkpackage 3: Time: 2 monthDepending on the evaluation results the detailed hard and software specification will be done.This includes:- detailed block diagrams- detailed hardware and software structure- interfaces for software implementation, hard and software co-design- test bench requirements and structure in order to simulate the final SOCWorkpackage 4: Time: 8 months- VHDL design implementation- C-Code software generation and implementation.- set up test bench for hard and software design simulation and verificationWorkpackage 5: Time: 4 monthLESubcontractor I- ASIC vendor gate level net list of SOC design and simulation test pattern- chip layout- back annotation simulation and design verification- scan test insertion and production test pattern- prototype board design and assembly- back annotation net list for design verification - SOC samples and volume productionWorkpackage 6: Time: 3 months- set prototype board into operation to verify the SOC hard and software- technical documentationMilestones:M1 Basic design specification and CPU selectionM2 Detailed hard and software specification, tool selectionM3 VHDL and Software designM4 Testbench generation, design verificationM5 Gate level net list, simulation patternM6 layout, post layout net list, production test patternM7 post layout simulationM8 samplesM9 SOC test with prototype boardM10 Documentation Ámbito científico social sciencesmedia and communicationsgraphic designnatural sciencescomputer and information sciencessoftwarenatural sciencescomputer and information sciencesinternetengineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcomputer hardwarecomputer processors Programa(s) FP5-IST - Programme for research, technological development and demonstration on a "User-friendly information society, 1998-2002" Tema(s) 1.1.2.-4.7.2 - Subsystems technologies Convocatoria de propuestas Data not available Régimen de financiación ACM - Preparatory, accompanying and support measures Coordinador LIESEGANG ELECTRONICS GMBH Aportación de la UE Sin datos Dirección MENGENDAMM 12 30177 HANNOVER Alemania Ver en el mapa Coste total Sin datos
