Objetivo The novel time-triggered architecture (TTA) is gaining growing acceptance in industry as a generic architecture for highly dependable hard real-time systems. It is therefore important for industry and society in general that the design decisions that are at the core of this architecture are validated by all possible means. It is the objective of the project to validate experimentally the system concepts of the TTA, taking a prototype TTP/C controller chip, developed within the ESPRIT project TTA, as the basis. The experiments determine the error-detection coverage of the TTA in a realistic application by using different hardware and software based fault-injection methods.Work description:FIT uses all applicable hardware and software based fault-injection methods to locate weaknesses in TTA and to search for and evaluate design alternatives to correct these weaknesses. VHDL and C-Sim simulation models, pin level, heavy-ion and software implemented fault-injection techniques will be applied.It is planned that the two-year project will be partitioned into four phases of six months each.In phase I the hypotheses to be tested will be defined. Fault-injection experiments for the different injection methods will be specified. The hardware/software set-up of the experiments will be described.In phase II hardware and software for the individual experiments will be set-up for a typical hard-real-time application, consisting of a TTA cluster with a node-under-test and a golden node.In phase III a first set of fault-injection experiments will be carried out. At the end of phase III results from the different injection experiments will be analysed individually and jointly to merge and globally interpret the results of all experiments. Based on this analysis the experiments for phase IV will be defined.In phase IV a second round of injection experiments will be carried out. At the end of this phase results will be analysed and interpreted and possible improvements in the fault-tolerance mechanisms of the TTA will be considered. Ámbito científico natural sciencescomputer and information sciencessoftware Programa(s) FP5-IST - Programme for research, technological development and demonstration on a "User-friendly information society, 1998-2002" Tema(s) 1.1.2.-5.1.2 - CPA2: Dependability in services and technologies Convocatoria de propuestas Data not available Régimen de financiación CSC - Cost-sharing contracts Coordinador TECHNIKUM KAERNTEN - VEREIN ZUR ERRICHTUNG DER FACHHOCHSCHULE KAERNTEN Aportación de la UE Sin datos Dirección VILLACHERSTRASSE 1 9800 SPITTAL AN DER DRAU Austria Ver en el mapa Coste total Sin datos Participantes (7) Ordenar alfabéticamente Ordenar por aportación de la UE Ampliar todo Contraer todo AB VOLVO Suecia Aportación de la UE Sin datos Dirección 405 08 GOETEBORG Ver en el mapa Coste total Sin datos CHALMERS TEKNISKA HOEGSKOLA AKTIEBOLAG Suecia Aportación de la UE Sin datos Dirección 412 96 GOETEBORG Ver en el mapa Coste total Sin datos CZECH TECHNICAL UNIVERSITY IN PRAGUE Chequia Aportación de la UE Sin datos Dirección ZIKOVA 4 166 36 PRAHA 6 Ver en el mapa Coste total Sin datos MOTOROLA GMBH Alemania Aportación de la UE Sin datos Dirección HEINRICH-HERTZ-STRASSE 1 65232 TAUNUSSTEIN Ver en el mapa Coste total Sin datos TECHNISCHE UNIVERSITAET WIEN - INSTITUT FUER TECHNISCHE INFORMATIK Austria Aportación de la UE Sin datos Dirección TREITLSTRASSE 3/3/182 1040 WIEN Ver en el mapa Coste total Sin datos TTTECH COMPUTERTECHNIK AG Austria Aportación de la UE Sin datos Dirección SCHOENBRUNNERSTRASSE 7 1040 WIEN Ver en el mapa Coste total Sin datos UNIVERSIDAD POLITECNICA DE VALENCIA España Aportación de la UE Sin datos Dirección CAMINO DE VERA S/N 46022 VALENCIA Ver en el mapa Coste total Sin datos
