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Reliability Enhancement of Scaled Programmable Non-Volatile Semiconductor Memories

Objective

This project addresses the technology for Non Volatile Memories, both embedded and stand-alone, for the 0.15µm generations and beyond. One of the main limitations is presently given by the difficulty in reducing the thickness of tunnel and interpoly dielectric, due to reliability problems, connected to the stress induced leakage, which in turn impacts the scalability of the memory cell and the programming speed. The target of the project is to achieve a reduction of 20-25% in the tunnel oxide thickness and in the interpoly dielectric equivalent thickness, while keeping the same reliability, achieved with present gate oxide thickness. The result will be achieved by an in depth investigation of the physical mechanisms causing the leakage currents, and its dependence on process parameters and programming conditions, and it will be demonstrated at the end of the project on large cell arrays by the industrial partners.

Call for proposal

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Coordinator

STMICROELECTRONICS S.R.L.
EU contribution
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Address
VIA OLIVETTI 2
20041 AGRATE BRIANZA
Italy

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Total cost
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Participants (4)