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NANOELECTRONIC DEVICES AND FAULT-TOLERANT ARCHITECTURES

Objetivo

This project aims at exploring cheap technologies that combines silicon nano-fabrication techniques and the emerging area of intra-molecular electronics to develop high-density memory arrays. The technology is based on the low temperature wafer bonding technique that will enable the combination in a high-density package of logic and analog devices fabricated with commercial CMOS technology with memory arrays. The 3-D configuration allows the use of fault-tolerant architectures that compensate for high device defect densities without increase of the chip area. The basic device concept is a nano-flash memory device in a hybrid Si-molecular configuration or in a purely molecular configuration. This project aims at exploring cheap technologies that combines silicon nano-fabrication techniques and the emerging area of intra-molecular electronics to develop high-density memory arrays. The technology is based on the low temperature wafer bonding technique that will enable the combination in a high-density package of logic and analogue devices fabricated with commercial CMOS technology with memory arrays. The 3-D configuration allows the use of fault-tolerant architectures that compensate for high device defect densities without increase of the chip area. The basic device concept is a nano-flash memory device in a hybrid Si-molecular configuration or in a purely molecular configuration.

OBJECTIVES
To develop a new inexpensive technology for the fabricating non-volatile memories based on a hybrid silicon and molecular nano-technology and combine it with mainstream CMOS technology using wafer bonding at low temperature to make 3-D stacks.
To develop fault-tolerant architectures suitable for low yield non-volatile memory device fabrication processes.
To develop high throughput nano-fabrication techniques using optical lithography and self limited etching techniques for Si nano-structure fabrication.
To investigate a range of molecules as room temperature charge storage elements and integrate them on top of a Si channel to demonstrate a non-volatile nano-flash memory device.

DESCRIPTION OF WORK
FRACTURE will implement memory devices that can be fabricated at a lower cost than current CMOS technology. For their fabrication we combine silicon nano-fabrication techniques that are realised by optical lithography -avoiding e-beam lithography or other serial lithographic techniques- and molecular electronic devices. The principle of our memory device is similar to floating-gate flash memories. Since memory cells are accompanied by read out electronics and logic units we envisage to fabricate these circuits on a substrate wafer together with the interconnects that address the memory devices. The memory devices are personalized on a thin Si film after bonding and removal by selective etching of a Silicon-On-Insulator wafer on top of the prefabricated CMOS circuit using "cold" processes that will not affect the underlying materials. Due to the poor expected fabrication yield of the target technologies fault tolerance is mandatory and is addressed in parallel with technology development. The proposed 3-D Architecture compensates for the increased chip area to accommodate fault-tolerant architectures

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Convocatoria de propuestas

Data not available

Régimen de financiación

CSC - Cost-sharing contracts

Coordinador

NATIONAL CENTRE FOR SCIENTIFIC RESEARCH "DEMOKRITOS"
Aportación de la UE
Sin datos
Dirección

15310 AGHIA PARASKEVI ATTIKIS
Grecia

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Coste total
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Participantes (3)