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SEMICONDUCTOR FREE NANOSCALE NON-VOLATILE ELECTRONICS AND MEMORIES BASED ON MAGNETIC TUNNEL JUNCTIONS

Objective

The actual active memory (mostly DRAM) is volatile, dissipates large amounts of energy owing to frequent refreshing and the requirement of individual capacitor for each memory. The overall thrust of this project is to develop two varieties of Tunnelling-Magnetic RAM (MRAM), namely the MIMRAM (Metalinsulator-Metal RAM) and the TTRAM (Tunnelling Transistor RAM) to the degree they have the capability to replace the currently available generations of RAM (based on semi-conductor technology). In the longer term, the basic science of this project also paves the way for replacing part of the hard disks with Tunnelling-MRAM. Compared to the first generation of MRAM, the MIMRAM (2-terminal) and the TTRAM (3-terminal) offer the advantage of small cell size in the 10 nm range and hence high packaging density, in conjunction with suppression of parasitic signal paths in read and write operation. The actual active memory (mostly DRAM) is volatile, dissipates large amounts of energy owing to frequent refreshing and the requirement of individual capacitor for each memory. The overall thrust of this project is to develop two varieties of Tunnelling-Magnetic RAM (MRAM), namely the MIMRAM (Metalinsulator-Metal RAM) and the TTRAM (Tunnelling Transistor RAM) to the degree they have the capability to replace the currently available generations of RAM (based on semi-conductor technology). In the longer term, the basic science of this project also paves the way for replacing part of the hard disks with Tunnelling-MRAM. Compared to the first generation of MRAM, the MIMRAM (2-terminal) and the TTRAM (3-terminal) offer the advantage of small cell size in the 10 nm range and hence high packaging density, in conjunction with suppression of parasitic signal paths in read and write operation.

OBJECTIVES
The desired characteristics of a memory cell for computer main memory are high speed, low power consumption and dissipation, non-volatility, high packing density and low cost. The overall thrust of NanoMEM is to develop two new varieties of Tunnelling-MRAM (Magnetic Random Access Memory) based on two terminal device MIMRAM (Metal- Insulator-Metal RAM) and three terminal device TTRAM (Tunnelling Transistor RAM). The objective of this proposal is to develop this new technology to the degree where it is capable to replace the currently available generation of RAM (which is based on semiconductor technology) in all applications. In the longer term, the basic science of this project also paves the way for replacing computer hard disks with Tunnelling-MRAs, thus affording much faster memory access times and no moving parts. Compared with other Tunnelling-MRAM architectures, the MIMRAM and TTRAM offer the advantage of small cell size and hence high packing density, in conjunction with suppression of parasctic signal paths in read and write operations. This will allow in a first step the length-scale of MRAM cells to be reduced from 0.35 microns to 100 nanometers and possibly below.

DESCRIPTION OF WORK
The project will be carried out in three phases, which are organised into six workpackages (WP1-WP6).

Phase 1 explores the properties of a single cell inside MRAM arrays. This will be addressed within WP1 (Magnetic switching), WP2 (Transport) and WP3 (Theory and Modelling). WP1 aims to provide reproducible and optimised switching fields in nanoscale tunnelling MRAM cells compatible with energy dissipation requirements and high frequency operations. WP2 address the suppression of parasitic signal paths in read/write operations, as well as explores techniques for enhancing reproducibly signal-to-noise of the memory cell read process. WP3 will bring theoretical input for WP1 and WP2 by modelling: (i) magnetic anisotropies of TRAM cells in order to reduce switching fields in small geometries and (ii) the spin-dependent tunnelling characteristics of 2 and 3 terminal TRAM cells.

Phase 2 tests the functionality of single cells inside the arrays as well as the novel architectures based on 2 and 3 terminal devices.

This will be addressed in WP4 (Technology) including the following issues:
(i) explore the limits of nanoscale lithography in the fabrication of small magnetic elements;
(ii) check the TRAM performance within accepted industry standard temperature specifications;
(iii) develop new strategies to handle three terminal devices. Effort must be paid on new line architectures, which include a third array of lines, and on an efficient read/write process.

In Phase 3, the MIMRAM and TTRAM devices are optimised with respect to cross-talk. This is addressed in WP5 (Evaluation) in which decisions are taken as to which system should be promoted in the second stage of the design. During the whole stage of this project, WP6 will insure the co-ordination of the research between the six partners as well as the achievement of the milestones and the completion of the deliverables. More important, an extensive exploitation plan of the results. ced by the industrial partners together with the coordinator of the project.

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

UNIVERSITE HENRI POINCARE NANCY 1
Address
Rue Lionnois 24 -30
54003 Nancy
France

Participants (4)

MAGDALEN COLLEGE
United Kingdom
Address
High Street
OX1 4AU Oxford
SIEMENS AKTIENGESELLSCHAFT
Germany
Address
Wittelsbacherplatz 2
80333 Muenchen
THALES
France
Address
45 Rue De Villiers
92200 Neuilly Sur Seine
UNIVERSITE LOUIS PASTEUR STRASBOURG I
France
Address
4, Rue Blaise Pascal
67070 Strasbourg