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High K Dielectric Film Growth

Project information

Grant agreement ID: IST-2000-29295

  • Start date

    1 July 2001

  • End date

    31 December 2004

Funded under:

FP5-IST

  • Overall budget:

    € 2 947 746

  • EU contribution

    € 1 628 539

Coordinated by:

UNIVERSITY COLLEGE CORK - NATIONAL UNIVERSITY OF IRELAND, CORK

Ireland

Objective

The need for atomic scale modelling into technology design has been evident for some time, as stated in the 1997 SIA Roadmap: "Continuum physics models and tools are no longer sufficient below 100 nm. Tools are needed for the physical and chemical processes at an atomic level".

In general, the level of expertise required to achieve atomic scale simulation is generally outside the capabilities of any single organisation. The HIKE project offers an innovative solution to this problem by a critical linking of semiconductor manufacturers, national research laboratories and academic laboratories to develop the simulation capabilities needed at atomic length scales.

The development of simulation tools within HIKE for chemical vapour deposition (CVD) and atomic layer deposition (ALD) for high k dielectric materials (hafnium and zirconium oxides) will provide process development engineers with the capability to directly tailor film growth and will provide them with an understanding of the exact mechanisms for deposition of their specific material systems. This allows for significant reduction in the number of calibration runs required during process development through identification of processing windows prior to experimentation phases. The further added benefit of simulation allowing development engineers to visualise deposition processes is a perhaps a less tangible benefit, but nonetheless is now recognised as of being of concrete value in the design stages of product development. Although not the main impetus of the project, the software to be developed and applied in support of the project goals represents a substantial step beyond the state of the art in technology computer aided design.

Objectives:
The HIKE project addresses issues pertaining to process design for new, high-k dielectric materials for gate oxide applications in sub 0.1 micron (100 nanometer) CMOS technologies. The project focuses on two new candidate materials, HfO2, Zr02 and the related Al2O3 oxide for barrier applications. The introduction of new gate materials for active device and memory applications is driven by the requirements for oxide layers. Reliability and device operability limitations due to high field gradients and large tunnelling currents pose severe restrictions for scaling of conventional MOS devices using SiO2 gate materials. High-k dielectric materials promise comparable electrical performance to silicon dioxide with thicker gate oxides, thereby reducing both tunnelling currents and electric field gradients. The objectives of the HIKE project are to develop advanced atomic scale models of film growth and to develop electrical models fro deca-nanometer devices.

Work description:
The technical workplan of the HIKE project consists of five workpackages, which are logically interrelated. The project is structured such that the first two workpackages (WP) address the fundamental chemistry of film growth and atomic layer deposition:
WP1 details the fundamental reaction steps and;
WP2 determines the governing rate equations. The following two workpackages employ the basic physics and chemistry data to study the details of the deposition processes;
WP3 addresses film growth from an atomic level, and;
WP4 addresses film growth from reactor and feature scale simulations. The final workpackage is concerned with the electrical and thermodynamical properties of the grown high-k films. Within the first workpackage, density functional theory (DFT) quantum chemistry studies of elementary reactions on Si (100) surface and on the grown surfaces will be performed. Within the second workpackage, the reaction mechanisms identified will be represented as rate equations assuming statistical rate theory. Rate constants and other kinetic data will be applied to model film growth and to determine event lists based upon activation energies and experimental data. Atomic scale models for the film growth will be used in kinetic Monte Carlo simulations within workpackage 3.

The kinetic Monte Carlo method is an event driven technique and eliminates the difficulties encountered when attempting to simulate process steps from molecular dynamics. The purpose of the fourth workpackage is to validate and explore the rate equations developed for thicker film CVD deposition (>1nm) and to examine the process ability of the new proposed oxide materials, where continuum simulation is valid and computationally less demanding. This further allows for model calibration for non-trivial deposition geometries. In the final workpackage 5, assessment of the quality of the new oxide materials in terms of electrical properties and thermodynamic stability will be performed.

Milestones:
Process definition for high K dielectric materials for three distinct applications in microelectronics device fabrication will be generated: MOSFET gate dielectrics, memories (DRAMs, EEPROMs) and high value integrated capacitors. TCAD simulation tools linking atomic scale, feature scale and reactor scale simulations will be developed and integrated into a user-defined interface.

Coordinator

UNIVERSITY COLLEGE CORK - NATIONAL UNIVERSITY OF IRELAND, CORK

Address

Western Road
Cork

Ireland

Participants (4)

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

France

FREESCALE HALBLEITER DEUTSCHLAND GMBH

Germany

INFINEON TECHNOLOGIES AG

Germany

UNIVERSITY COLLEGE LONDON

United Kingdom

Project information

Grant agreement ID: IST-2000-29295

  • Start date

    1 July 2001

  • End date

    31 December 2004

Funded under:

FP5-IST

  • Overall budget:

    € 2 947 746

  • EU contribution

    € 1 628 539

Coordinated by:

UNIVERSITY COLLEGE CORK - NATIONAL UNIVERSITY OF IRELAND, CORK

Ireland