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Energy-aware System-on-Chip design of the HIPERLAN/2 standard

Energy-aware System-on-Chip design of the HIPERLAN/2 standard

Objective

EASY deals with the implementation of a low power/cost System-on-Chip (SoC) that handles both the baseband modem and critical functionality of the DLC layer of the very promising and emerging HIPERLAN/2 European standard. No such a SoC device exists in the market. The implementation will contain the hardware-software system's mapping, the development of the real-time software for the system's parts that will be executed on the used processors, the design of custom hardware blocks which will implement critical system's parts, the integration of the hardware-software blocks, the board development and the demonstration of the system. During the project, a low-power design methodology for wireless protocol applications, accompanied with prototype tools, will be developed. This methodology contains novel power optimisation techniques related to the system's embedded software, the hardware-software mapping, the data transfer/storage and the memory/bus architecture.

Objectives:
The main objectives of the EASY project are:
- To develop a cost/power efficient heterogeneous System-on-Chip processor, that handles both the baseband modem and critical functionality of the DLC layer of the HIPERLAN/2 protocol stack.
- To develop a low-power design methodology for the low-power implementation of wireless protocol applications on heterogeneous System-on-Chip platforms. This methodology will contain novel power optimisation techniques related to the system's embedded software, the hardware-software mapping procedure, the data transfer and storage, and the memory/bus architecture.
- To develop prototype tools, based on the developed low-power design methodology.
- To exploit and disseminate the results of the project.

Work description:
The EASY project aims at developing a power/cost efficient System-on-Chip (SoC) implementation of the HIPERLAN/2 standard. The design flow that will be followed for the development of the SoC will start with the definition of the system's specifications, the development of a high-level system model, and the definition of the system's architecture. The procedure will be continued with a power-conscious mapping of the system's functionality to a number of software blocks and custom blocks (hardware). Then, the real-time embedded software that implements critical functionality of the protocol's DLC layer and baseband modem, will be developed interactively with the design of the custom blocks. In the SW development, high-level languages (like SDL, UML, System C), and C/C++ coding will be used. A commercial RTOS will also be used for the coding. The custom blocks will initially be described in high-level. Then, VHDL coding/simulation at the RT level, synthesis, optimisation and gate-level simulation will be applied to each of the custom blocks, first, and at the integration level then. The next steps include low-level hardware/software co-simulation, floor planning, placement and routing, verification, layout and SoC fabrication. Finally, the EASY board will be developed for the HIPERLAN/2 system demonstration. During the project, a systematic methodology that will integrate, in a single flow, different approaches for power optimisation at the system level and the real-time software development for heterogeneous SoC platforms, customized to the special features of the target application domain and accompanied by prototype tools will be developed. This aims to explore and optimise in terms of power the system's embedded software, reduce the power consumption due to data storage and transfer by applying algorithmic transformations, and implement a power-efficient memory organization and bus interface. Strong exploitation and dissemination plans will be followed.

Milestones:
The basic milestones and expected results of the EASY project are:
- An advanced low power/cost System-on-Chip that handles the baseband modem and the critical functionality of the DLC layer of the HIPERLAN/2 standard (hardware and real-time software parts).
- A systematic methodology (accompanied with prototype tools) which contains optimisation techniques concerning the system's embedded software, the hardware-software mapping, the data transfer and storage, the memory architecture and the bus interface.
- Dissemination and exploitation or the project results.

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Coordinator

INTRACOM S.A. HELLENIC TELECOMMUNICATIONS AND ELECTRONICS INDUSTRY

Address

Odos Markopoulou 19,5km Ktirio B5 Mark X
19002 Peania - Attiki

Greece

Administrative Contact

Labros BISDOUNIS

Participants (7)

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ARISTOTLE UNIVERSITY OF THESSALONIKI

Greece

BULLDAST S.R.L.

Italy

FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.

Germany

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW

Belgium

POLITECNICO DI TORINO

Italy

STMICROELECTRONICS S.R.L.

Italy

UNIVERSITY OF PATRAS

Greece

Project information

Grant agreement ID: IST-2000-30093

  • Start date

    1 September 2001

  • End date

    28 February 2005

Funded under:

FP5-IST

  • Overall budget:

    € 4 075 258

  • EU contribution

    € 2 222 627

Coordinated by:

INTRACOM S.A. HELLENIC TELECOMMUNICATIONS AND ELECTRONICS INDUSTRY

Greece