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Compact modelling of on-chip passive structures at high frequencies

Objective

To achieve data transmission at higher bitrates, the chip clock speed continuously increases. Modelling software taking into account high-frequency effects is crucial for good understanding of the future VLSI designs. The development of such code is the main goal of CODESTAR. First a detailed analysis of the test structure is carried out using an electromagnetic field solver. The outcome of the field solver is a full net list. This net list will be too large to be useful and therefore a systematic reduction of the net list must be done (i.e. reduced-order modelling). The resulting compact equivalent limped-element model is inserted back into full design scheme and the design cycle can be pursued. Parallel fabrication, characterisation and evaluation of dedicated test structures is carried out, in order to validate the CODESTAR code.

OBJECTIVES
The main goal of the CODESTAR project is the development of a code dedicated for the electromagnetic simulation of passive on-chip structure resulting in a small simulation network. First a detailed analysis of the test is carried out using an electromagnetic field solver. The outcome of the field solver is a full net list describing the detailed characteristics of the passive structure. This net list will be too large to be useful and therefore a systematic reduction of the net list must be done (i.e. reduced-order modelling). The resulting compact equivalent lumped-element model is inserted back into the full design scheme and the design cycle can be pursued. Parallel fabrication, characterisation and evaluation of dedicated test structures is carried out, in order to validate the CODESTAR code. The matching between experimental and CODESTAR simulation results is the measure of the project success.

DESCRIPTION OF WORK
A critical part of a passive on-chip design is submitted to a detailed analysis by the CODESTAR-code.- The first part of the project deals with the detailed analysis of the critical structure using an electromagnetic field solver. Three types of field solvers are considered and compared, being the finite-difference-time-domain solver, the finite-integration solver and a lattice-gauge solver. The outcome of the field solvers are a full net list including the net list parameters.- In general, this net list will be too large to be useful for inclusion in the design database and therefore a systematic reduction of the net list must be carried out i.e. application of reduced-order modelling (ROM). After having obtained a sufficiently compact equivalent lumped-element model, the result is inserted back into the full design scheme and the interconnect design cycle will be continued. The emphasis of this work will be on the development of new techniques like the Laguerre-SVD and the two-step Lanczos technique and their connection with the different field solving techniques.- Parallel with this code development process, dedicated test structures are designed and evaluated to validate the CODESTAR code. The test-cases will attempt to capture the complexity of realistic interconnect structures, will highlight the limits of present CAD tools and allow to assess the enhancements brought by the new tool created in this project.- The resulting software will be used on a day-to-day basis at all partner sited. The research results will be disseminated in the academic community through workshops, conferences, demonstrators. All patent-sensitive technology will be protected. The industrial interest for the resulting CODESTAR code is evaluated and a technological implementation plan is created.

Coordinator

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW

Address

Kapeldreef 75
3001 Leuven

Belgium

Administrative Contact

Wim SCHOENMAKER

Participants (6)

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AUSTRIAMICROSYSTEMS AG

Austria

MAGWEL NV

Belgium

PHILIPS ELECTRONICS NEDERLAND B.V.

Netherlands

TECHNISCHE UNIVERSITEIT EINDHOVEN

Netherlands

UNIVERSITATEA POLITEHNICA DIN BUCURESTI

Romania

UNIVERSITEIT GENT

Belgium

Project information

Grant agreement ID: IST-2001-34058

  • Start date

    1 March 2002

  • End date

    31 August 2004

Funded under:

FP5-IST

  • Overall budget:

    € 2 603 980

  • EU contribution

    € 1 711 730

Coordinated by:

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW

Belgium