Cel To achieve data transmission at higher bitrates, the chip clock speed continuously increases. Modelling software taking into account high-frequency effects is crucial for good understanding of the future VLSI designs. The development of such code is the main goal of CODESTAR. First a detailed analysis of the test structure is carried out using an electromagnetic field solver. The outcome of the field solver is a full net list. This net list will be too large to be useful and therefore a systematic reduction of the net list must be done (i.e. reduced-order modelling). The resulting compact equivalent limped-element model is inserted back into full design scheme and the design cycle can be pursued. Parallel fabrication, characterisation and evaluation of dedicated test structures is carried out, in order to validate the CODESTAR code.OBJECTIVESThe main goal of the CODESTAR project is the development of a code dedicated for the electromagnetic simulation of passive on-chip structure resulting in a small simulation network. First a detailed analysis of the test is carried out using an electromagnetic field solver. The outcome of the field solver is a full net list describing the detailed characteristics of the passive structure. This net list will be too large to be useful and therefore a systematic reduction of the net list must be done (i.e. reduced-order modelling). The resulting compact equivalent lumped-element model is inserted back into the full design scheme and the design cycle can be pursued. Parallel fabrication, characterisation and evaluation of dedicated test structures is carried out, in order to validate the CODESTAR code. The matching between experimental and CODESTAR simulation results is the measure of the project success.DESCRIPTION OF WORKA critical part of a passive on-chip design is submitted to a detailed analysis by the CODESTAR-code.- The first part of the project deals with the detailed analysis of the critical structure using an electromagnetic field solver. Three types of field solvers are considered and compared, being the finite-difference-time-domain solver, the finite-integration solver and a lattice-gauge solver. The outcome of the field solvers are a full net list including the net list parameters.- In general, this net list will be too large to be useful for inclusion in the design database and therefore a systematic reduction of the net list must be carried out i.e. application of reduced-order modelling (ROM). After having obtained a sufficiently compact equivalent lumped-element model, the result is inserted back into the full design scheme and the interconnect design cycle will be continued. The emphasis of this work will be on the development of new techniques like the Laguerre-SVD and the two-step Lanczos technique and their connection with the different field solving techniques.- Parallel with this code development process, dedicated test structures are designed and evaluated to validate the CODESTAR code. The test-cases will attempt to capture the complexity of realistic interconnect structures, will highlight the limits of present CAD tools and allow to assess the enhancements brought by the new tool created in this project.- The resulting software will be used on a day-to-day basis at all partner sited. The research results will be disseminated in the academic community through workshops, conferences, demonstrators. All patent-sensitive technology will be protected. The industrial interest for the resulting CODESTAR code is evaluated and a technological implementation plan is created. Dziedzina nauki natural sciencesphysical scienceselectromagnetism and electronicselectromagnetismnatural sciencescomputer and information sciencessoftwarenatural sciencescomputer and information sciencesdatabases Program(-y) FP5-IST - Programme for research, technological development and demonstration on a "User-friendly information society, 1998-2002" Temat(-y) 2001-4.8.2 - Microelectronics technologies: processes, equipment and devices Zaproszenie do składania wniosków Data not available System finansowania CSC - Cost-sharing contracts Koordynator INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW Wkład UE Brak danych Adres KAPELDREEF 75 3001 LEUVEN Belgia Zobacz na mapie Koszt całkowity Brak danych Uczestnicy (6) Sortuj alfabetycznie Sortuj według wkładu UE Rozwiń wszystko Zwiń wszystko AUSTRIAMICROSYSTEMS AG Austria Wkład UE Brak danych Adres SCHLOSS PREMSTAETTEN, TOBELBADERSTRASSE 30 8141 UNTERPREMSTAETTEN Zobacz na mapie Koszt całkowity Brak danych MAGWEL NV Belgia Wkład UE Brak danych Adres KAPELDREEF, 75 3001 HEVERLEE Zobacz na mapie Koszt całkowity Brak danych PHILIPS ELECTRONICS NEDERLAND B.V. Niderlandy Wkład UE Brak danych Adres BOSCHDIJK 525 5621 JG EINDHOVEN Zobacz na mapie Koszt całkowity Brak danych TECHNISCHE UNIVERSITEIT EINDHOVEN Niderlandy Wkład UE Brak danych Adres Den Dolech 2 EINDHOVEN Zobacz na mapie Linki Strona internetowa Opens in new window Koszt całkowity Brak danych UNIVERSITATEA POLITEHNICA DIN BUCURESTI Rumunia Wkład UE Brak danych Adres SPLAIUL INDEPENDENTEI 313 77206 BUCHAREST Zobacz na mapie Koszt całkowity Brak danych UNIVERSITEIT GENT Belgia Wkład UE Brak danych Adres SINT PIETERSNIEUWSTRAAT 25 9000 GENT Zobacz na mapie Koszt całkowity Brak danych
