Objectif Much world-wide effort is being devoted to research into nanoelectronic and nanophotonics devices, but less effort is being applied to examining system architectures, which might use these devices to best advantage. Such research is needed, so that present-day increases in computing power can be extended into the future. To achieve such increases will be a major technological challenge, and proactive research and planning is needed now. Some unanswered technical questions are: Can devices be assembled into ultra-high density circuits? Are any of these devices fundamentally unsuitable? Will factors such as size variations affect performance? Can manufacturing faults and transient errors be overcome using fault tolerance? Will the circuits have better performance than CMOS-type circuits? Will nanoscale circuits be cheaper than CMOS? Besides these technical questions, two other questions must also be asked: What systems research is being carried out now, and what gaps are there? - and are there enough trained people in Europe who are capable of solving these problems? Some but not all of these questions are being looked at under existing EC initiatives.We therefore propose a survey which, starting from the existing EC Nanoelectronics Roadmap, would report on existing European expertise in the following areas:1. existing and proposed nanoelectronic/photonic devices;2. small circuits: theory and practice;3. ultralarge circuits: theory and practice;4. conventional architectural concepts;5. unconventional concepts;6. new concepts;7. known problems;8. 'system on a chip' and 3D systems;9. applications: performance requirements;10. availability and training of human resources.The report will suggest topics where further effort might be applied, ranging from basic theoretical research, through device/circuit fabrication techniques, to possible training and research workshops. Information will also be provided on US and Pacific Rim activity. Champ scientifique engineering and technologynanotechnologynanophotonicsengineering and technologynanotechnologynanoelectronics Mots‑clés Nanotechnology Risk Assessment Programme(s) FP6-IST - Information Society Technologies: thematic priority under the specific programme "Integrating and strengthening the European research area" (2002-2006). Thème(s) IST-2002-2.3.1.1 - Pushing the limits of CMOS, preparing for post-CMOS Appel à propositions Data not available Régime de financement SSA - Specific Support Action Coordinateur UNIVERSITY COLLEGE LONDON Contribution de l’UE Aucune donnée Adresse GOWER STREET WC1E 6BT LONDON Royaume-Uni Voir sur la carte Coût total Aucune donnée Participants (2) Trier par ordre alphabétique Trier par contribution de l’UE Tout développer Tout réduire BERGISCHE UNIVERSITAET WUPPERTAL Allemagne Contribution de l’UE Aucune donnée Adresse GAUSS-STRASSE 20 42097 WUPPERTAL Voir sur la carte Coût total Aucune donnée TECHNISCHE UNIVERSITEIT DELFT Pays-Bas Contribution de l’UE Aucune donnée Adresse Lorentzweg 2628 CJ Delft Voir sur la carte Coût total Aucune donnée
