Objectif The HIDING DIES project aims to develop a highly innovative technology for embedding active chips into high-density printed circuit boards. This 3-dimensional integration will enable a high degree of miniaturization, improved electrical and thermal performance for mobile and communication products. The technological steps are bonding of thin chips (50 µm) on multilayer substrates, embedding of the chips by vacuum lamination of a dielectric layer (RCC), followed by laser drilling of via holes to the chip contacts and to the substrate and finally metallization of vias and conductor lines. For a further increase of functional density integrated passive components can be combined with the chip embedding. The resulting sub-systems with integrated components additionally allow assembly of surface mount devices on the bottom and top surface. All required process steps will be based on existing technologies, however their combination to a cost-effective high-yielding technology require significant scientific and technological research. Besides the process development, a detailed understanding of thermo-mechanical, thermal and electrical performance of such integrated systems has to be achieved. Furthermore development effort has to be made to explore technological limits by handling and bonding very large and very thin chips (50 µm) and by stacking multiple layers with integrated components.The achievement of the development goals will be assessed using two demonstrators, specified by end users. A sensor device combines a surface mounted MEMS chip with embedded control circuits, resulting in an extremely small footprint.The other demonstrator is a power RF application. Target is to create a miniaturized module with excellent electrical and heat conducting properties. With the IC's embedded in the substrate, short connections to filter structures and assembled discrete SMD's at the surface, a compact miniature module can be created. Champ scientifique engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringsensorsnatural sciencesphysical sciencesopticslaser physics Mots‑clés Nanotechnology Risk Assessment Programme(s) FP6-IST - Information Society Technologies: thematic priority under the specific programme "Integrating and strengthening the European research area" (2002-2006). Thème(s) IST-2002-2.3.1.2 - Micro and nano-systems Appel à propositions Data not available Régime de financement STREP - Specific Targeted Research Project Coordinateur TECHNISCHE UNIVERSITAET BERLIN Contribution de l’UE Aucune donnée Adresse Gustav-Meyer-Allee 25 13355 BERLIN Allemagne Voir sur la carte Coût total Aucune donnée Participants (6) Trier par ordre alphabétique Trier par contribution de l’UE Tout développer Tout réduire AT AND S AUSTRIA TECHNOLOGIE AND SYSTEMTECHNIK AKTIENGESELLSCHAFT Autriche Contribution de l’UE Aucune donnée Adresse Voir sur la carte Coût total Aucune donnée CHEMNITZER WERKSTOFFMECHANIK GMBH Allemagne Contribution de l’UE Aucune donnée Adresse Voir sur la carte Coût total Aucune donnée DATACON SEMICONDUCTOR EQUIPMENT GMBH Autriche Contribution de l’UE Aucune donnée Adresse Voir sur la carte Coût total Aucune donnée INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW Belgique Contribution de l’UE Aucune donnée Adresse St-Pieternieuwstraat 41 B-9000 Gent Voir sur la carte Coût total Aucune donnée NOKIA CORPORATION Finlande Contribution de l’UE Aucune donnée Adresse Voir sur la carte Coût total Aucune donnée PHILIPS ELECTRONICS NEDERLAND B.V. Pays-Bas Contribution de l’UE Aucune donnée Adresse Glaslaan 2 5600 MD Eindhoven Voir sur la carte Coût total Aucune donnée