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Photonic Interconnect Layer on CMOS by Wafer-Scale Integration

Objective

For future generation electronic circuits a severe bottleneck is expected on the global interconnect level. One of the most promising solutions is the use of an optical interconnect layer. Therefore, PICMOS will demonstrate the feasibility of adding a photonic interconnect layer on top of silicon ICs. This interconnect layer will be fabricated by a combination of wafer bonding and wafer-scale processing steps. It will be planar and will be built from a high-density passive optical wiring circuit integrated with InP-based sources and detectors using a wafer bonding approach.

Two different integration strategies will be investigated: a wafer-to-wafer bond technology where the photonic interconnect layer is fabricated in parallel with the electronic circuits wafer and where both wafers are subsequently bonded together and an above-IC approach where the interconnect layer is fabricated directly on top of the electronic circuits. For the first approach, SOI-waveguides allowing for very high-density wiring will be developed. For the above-IC approach, an innovative type of high-contrast polymer waveguides compatible with CMOS back-end processing will be developed. Both types of waveguides will be fabricated using standard CMOS-processing techniques.

The III-V epi material for the active photonic devices will be bonded on top of the waveguide circuits and the substrate will be removed. The active devices will be defined in the remaining membrane. In all fabrication steps, only waferscale technologies will be employed with the only exception made for the bonding of the III-V semiconductor material. Because of the large size difference between silicon and InP wafers and the limited space occupied by the active photonic devices, a rapid die-to-wafer bonding step will be developed for this step. In parallel with the technological oriented work, system studies will define application domains for PICMOS and generic parameter specifications for all subcomponents.

Funding Scheme

STREP - Specific Targeted Research Project

Coordinator

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
Address
Kapeldreef 75
3001 Leuven
Belgium

Participants (8)

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
France
Address
3, Rue Michel-ange
75794 Paris Cedex 16
COMMISSARIAT A L'ENERGIE ATOMIQUE
France
Address
Batiment Le Ponant D, 25 Rue Leblanc
75015 Paris Cedex 15
ECOLE CENTRALE DE LYON - CRELYMO
France
Address
36, Avenue Guy De Collongue
69134 Ecully Cedex
INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON
France
Address
20, Avenue Albert Einstein
69621 Villeurbanne Cedex
NATIONAL CENTRE FOR SCIENTIFIC RESEARCH "DEMOKRITOS"
Greece
Address
Patriarchou Gregoriou Street
15310 Aghia Paraskevi Attikis
STMICROELECTRONICS SA
France
Address
29 Boulevard Romain Rolland
92120 Montrouge
TECHNISCHE UNIVERSITEIT EINDHOVEN
Netherlands
Address
Den Dolech 2
5600 MB Eindhoven
TRACIT TECHNOLOGIES
France
Address
Centr'alp, 52 Rue Du Corporat
38430 Moirans