CORDIS
EU research results

CORDIS

English EN
High-performance embedded architectures and compilers

High-performance embedded architectures and compilers

Objective

HiPEAC addresses the design and implementation of high-performance commodity computing devices in the 10+ year horizon, covering the processor design, the optimising compiler infrastructure, and the evaluation of upcoming applications made possible by the increased computing power of future devices. The objectives of HiPEAC are to ensure the visibility of European institutions in the high performance embedded marked, and to promote the integration of research efforts in a common direction. Visibility will be achieved through dissemination of our work under a common HiPEAC label that will raise the awareness of our coordinated research effort. Integration will be achieved through a set of coordinated actions targeted at building a strong community of researchers, and the adherence to a commonly agreed research roadmap that will be strongly influenced by European industry and leading worldwide research institutions.

HiPEAC will also provide the means for easy collaboration among members, and rapid dissemination of knowledge among the community, as well as strengthening the relationships between academia and European industry. HiPEAC brings together the leading European experts in computer architecture, coordinating -for the first time- their research effort. HiPEAC will build up European strength by spreading knowledge and expertise to engineers and students, and by transferring this expertise to industry, with the goal of making Europe the worldwide leader in high-performance embedded processor architectures.

The end target is to create a virtual centre of excellence in high-performance compilers and architectures for embedded processors. This centre will gather the world's largest critical mass of researchers, generate world-leading results in embedded architectures, and offer the best discussion forums on our topics of influence, becoming a focal point in the fields of computer architecture and optimizing compilers at the maximum level.

Leaflet | Map data © OpenStreetMap contributors, Credit: EC-GISCO, © EuroGeographics for the administrative boundaries

Coordinator

UNIVERSITAT POLITECNICA DE CATALUNYA

Address

Jordi Girona 31
08034 Barcelona

Spain

Administrative Contact

Participants (13)

Sort alphabetically

Expand all

ARM LIMITED

United Kingdom

CHALMERS TEKNISKA HOEGSKOLA AB

Sweden

FOUNDATION FOR RESEARCH AND TECHNOLOGY HELLAS

Greece

IBM ISRAEL - SCIENCE AND TECHNOLOGY LTD

Israel

INFINEON TECHNOLOGIES AG

Germany

INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE

France

INSTITUT NATIONALE DE LA RECHERCHE AGRONOMIQUE INRA

France

STMICROELECTRONICS SRL

Italy

TECHNISCHE UNIVERSITEIT DELFT

Netherlands

THE UNIVERSITY OF EDINBURGH

United Kingdom

UNIVERSITA DI PISA

Italy

UNIVERSITAET AUGSBURG

Germany

UNIVERSITEIT GENT

Belgium

Project information

Grant agreement ID: 004408

  • Start date

    1 September 2004

  • End date

    31 December 2008

Funded under:

FP6-IST

Coordinated by:

UNIVERSITAT POLITECNICA DE CATALUNYA

Spain