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Verification and validation of embedded system design workbench that is how to make sure that systems controlled by intelligent electronic chips will satisfy certain safety conditions

Objective

Embedded Systems are built on top of SW and HW capabilities. It is economically convenient to exploit common HW solutions among different applications, through the use of platform based design and architectures based on configurable logic HW. A recurrent problem for the HW integrator is to validate a specific architecture without the knowledge of the final application(s). The development of SW/HW co-simulation methods and related coverage metrics applied at this field are vital to achieve the verification of the embedded system platform.

The verification framework is often constituted by a mix of SW, TLM, RTL. In this context the main goal of the VERTIGO project is the development of a systematic methodology to combine a simulation-based approach (dynamic verification) together with formal verification methods (static verification) integrated into an IP-cores and platform based design flow, for the purpose of producing a SW kit applied to the platform validation.

Such system level based design verification flow must solve three main problems:
- Verification of the correct interaction between all IP-cores and of the system in the networked environment
- Production of a SW layer for the purpose of the embedded platform test
- Verification of the correct modelling of system-level IP-cores and their correct mapping into RTL descriptions.

The solution of these problems require to correctly integrate verification and designing into a robust flow, to smoothly move from verification languages (e.g., SystemC, System Verilog) to RTL languages, to combine dynamic and static verification techniques, thus exploiting and composing a variety of verification engines (e.g., SAT, High-Level Decision Diagrams, Hierarchical Petri Nets, EFSMs, etc.).

VERTIGO addresses a new generation of technologies and tools for modelling and testing embedded platforms that will be the foundation for a viable and cost-efficient mapping of HW/SW systems embedded in intelligent devices.

Funding Scheme

STREP - Specific Targeted Research Project
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Coordinator

STMICROELECTRONICS SRL
Address
Via Olivetti 2
20041 Agrate Brianza
Italy

Participants (6)

AERIELOGIC SARL
France
Address
4 Avenue De Cambridge, Immeuble Odysse, Citis
14200 Herouville St Clair
LINKÖPINGS UNIVERSITET
Sweden
Address
Campus Valla
Linköping
TALLINNA TEHNIKAUELIKOOL
Estonia
Address
Ehitajate Tee 5
19086 Tallinn
TRANSEDA SYSTEMS LTD
United Kingdom
Address
Swallowfield House, Bath Road, Froxfield
SN8 3LD Marlborough
UNIVERSITA DEGLI STUDI DI VERONA
Italy
Address
Via Dell' Artigliere 8
37129 Verona
UNIVERSITY OF SOUTHAMPTON
United Kingdom
Address
Highfield
SO17 1BJ Southampton