Obiettivo Embedded Systems are built on top of SW and HW capabilities. It is economically convenient to exploit common HW solutions among different applications, through the use of platform based design and architectures based on configurable logic HW. A recurrent problem for the HW integrator is to validate a specific architecture without the knowledge of the final application(s). The development of SW/HW co-simulation methods and related coverage metrics applied at this field are vital to achieve the verification of the embedded system platform.The verification framework is often constituted by a mix of SW, TLM, RTL. In this context the main goal of the VERTIGO project is the development of a systematic methodology to combine a simulation-based approach (dynamic verification) together with formal verification methods (static verification) integrated into an IP-cores and platform based design flow, for the purpose of producing a SW kit applied to the platform validation.Such system level based design verification flow must solve three main problems:- Verification of the correct interaction between all IP-cores and of the system in the networked environment- Production of a SW layer for the purpose of the embedded platform test- Verification of the correct modelling of system-level IP-cores and their correct mapping into RTL descriptions.The solution of these problems require to correctly integrate verification and designing into a robust flow, to smoothly move from verification languages (e.g. SystemC, System Verilog) to RTL languages, to combine dynamic and static verification techniques, thus exploiting and composing a variety of verification engines (e.g. SAT, High-Level Decision Diagrams, Hierarchical Petri Nets, EFSMs, etc.).VERTIGO addresses a new generation of technologies and tools for modelling and testing embedded platforms that will be the foundation for a viable and cost-efficient mapping of HW/SW systems embedded in intelligent devices. Programma(i) FP6-IST - Information Society Technologies: thematic priority under the specific programme "Integrating and strengthening the European research area" (2002-2006). Argomento(i) IST-2005-2.5.3 - Embedded systems Invito a presentare proposte Data not available Meccanismo di finanziamento STREP - Specific Targeted Research Project Coordinatore STMICROELECTRONICS SRL Contributo UE Nessun dato Indirizzo VIA OLIVETTI 2 20041 AGRATE BRIANZA Italia Mostra sulla mappa Costo totale Nessun dato Partecipanti (6) Classifica in ordine alfabetico Classifica per Contributo UE Espandi tutto Riduci tutto AERIELOGIC SARL Francia Contributo UE Nessun dato Indirizzo 4 AVENUE DE CAMBRIDGE, IMMEUBLE ODYSSE, CITIS 14200 HEROUVILLE ST CLAIR Mostra sulla mappa Costo totale Nessun dato LINKÖPINGS UNIVERSITET Svezia Contributo UE Nessun dato Indirizzo Campus Valla LINKÖPING Mostra sulla mappa Costo totale Nessun dato TALLINNA TEHNIKAUELIKOOL Estonia Contributo UE Nessun dato Indirizzo EHITAJATE TEE 5 19086 TALLINN Mostra sulla mappa Costo totale Nessun dato TRANSEDA SYSTEMS LTD Regno Unito Contributo UE Nessun dato Indirizzo SWALLOWFIELD HOUSE, BATH ROAD, FROXFIELD SN8 3LD MARLBOROUGH Mostra sulla mappa Costo totale Nessun dato UNIVERSITA DEGLI STUDI DI VERONA Italia Contributo UE Nessun dato Indirizzo VIA DELL' ARTIGLIERE 8 37129 VERONA Mostra sulla mappa Costo totale Nessun dato UNIVERSITY OF SOUTHAMPTON Regno Unito Contributo UE Nessun dato Indirizzo HIGHFIELD SO17 1BJ SOUTHAMPTON Mostra sulla mappa Costo totale Nessun dato