An existing parallel execution model for Prolog on shared memory machines is being refined and implemented with a view to industrial exploitation. In addition, the project is designing more advanced models for executing Prolog in parallel on multiprocessor architectures, focusing particularly on transputer-based hardware.
An existing parallel execution model for Prolog on shared memory machines is being refined and implemented with a view to industrial exploitation. In addition, the project is designing more advanced models for executing Prolog in parallel on multiprocessor architectures, focussing particularly on transputer based hardware.
1 model will implement a combination of OR-parallelizm with dependent AND-parallelizm via a shared wirtual address space, while another model will implement OR-parallelizm and possibly AND-parallelizm via communicating processes. The models will be compared on the basis of how well they perform in large scale applications.
Simulation studies will be made to investigate how the software models can best be supported by hardware, with particular reference to architectures based on the transputer or similar principles.
Finally, an extension of Prolog will be defined and implemented that further exploits the potential of these parallel models. The ultimate aim is to have a language and implementation that combines the capabilities of the 3 existing classes of logic programming languages.

Prototypes for AND-parallelizm and OR-parallelizm on shared memory machines have been implemented, and a more advanced prototype including both types of parallelizm is in preparation. Specification and architecture design for a data diffusion machine implementation has been performed, and a possible model on a transputer based architecture has been explored. Results so far involve improvements in garbage collection and the definition of a core Prolog language for parallel execution.
One model will implement a combination of OR-parallelism with dependent AND-parallelism via a shared virtual address space, while another model will implement OR-parallelism and possibly AND-parallelism via communicating processes. The models will be compared on the basis of how well they perform in large-scale applications.

Simulation studies will be made to investigate how the software models can best be supported by hardware, with particular reference to architectures based on the transputer or similar principles.

Finally, an extension of Prolog will be defined and implemented that further exploits the potential of these parallel models. The ultimate aim is to have a language and implementation that combines the capabilities of the three existing classes of logic programming languages.